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 2.6. Endian Order

The Power ISA supports both big-endian and little-endian byte-ordering modes. Book I of the Power ISA describes these modes. However, the CAIA only supports big-endian byte ordering for accessing the registers defined in the CAIA document except where noted.

Specifically:

  • The POWER service layer (PSL) registers described in the CAIA only support big-endian byte ordering. The CAIA does not support accessing these registers in little-endian byte-ordering format. To access the PSL registers with little-endian byte ordering, little-endian system software must perform a byte swap.

  • The AFU descriptor registers described in the CAIA only support big-endian byte ordering. The CAIA does not support accessing these registers in little-endian byte-ordering format.

  • The PSL supports both little-endian and big-endian AFUs (except for the AFU descriptor registers). The big-endian limitation only applies to the registers defined in this CAIA document, which include the AFU descriptor registers contained in the AFU.

  • Data transfers between the host system and the AFU are simply byte moves without regard to the numerical significance of any byte. Thus, the AFU endian support is implementation-dependent.

Exception: The bit and byte ordering in the PCIe configuration space is little endian to maintain consistency with the PCIe architecture. This is the main exception to the big-endian byte ordering support provided by the CAIA. See Chapter 12, PCIe® Configuration Overview for more information.


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