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 9.2. Segment Lookaside Buffer Management

 The CAIA provides a set of MMIO registers to manage the SLBs in a PSL. These MMIO registers provide the same functions for a PSL MMU as the Power ISA instructions provide for a POWER processor MMU. That is, the following registers mimic the source operands of the Power ISA SLB management instructions (slbie and slbia ):


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