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 Chapter 9. Storage Addressing

Storage addressing of the Coherent Accelerator Interface Architecture (CAIA) is compatible with the Power ISA virtual memory architecture. The memory management unit (MMU) in the PSL employs the same basic mechanism as the Power ISA to process an effective address provided by an accelerator.

To enable translations of the effective addresses used by an accelerator, set the Relocate (R) bit of the PSL State Register (PSL_SR_An) to '1'.

Two steps are required to convert an effective address to a real address:

  1. Convert the effective address to a virtual address. The conversion to a virtual address uses a storage segment. The MMU in the PSL differs from the Power ISA in how the storage segments are accessed. In the Power ISA, the storage segments are provided by system software using processor instructions to load a segment lookaside buffer (SLB). For the PSL, the storage segments are in a hardware-accessed segment table located in main storage. The PSL searches the segment table for the storage segment to use for each translation. For the CAIA, the SLB is a hardware caching structure for the segment table. For both the Power ISA and the PSL, coherency of the SLB is maintained by system software.

  2. Convert the virtual address to a real address. The conversion of a virtual address to a real address uses a page table in main storage. The page table format and the conversion process are described in Power ISA, Book III .

 To enhance performance of effective to virtual conversions, most implementation provide a segment lookaside buffer (SLB). The SLB is, basically, a special cache for keeping the recently used segment table entries (STEs). The SLB need not be kept consistent with the hardware-accessed segment table in main storage. Coherency of the SLB is maintained by system software using the MMIO register provided by the PSL. All implementations must support an effective-to-virtual-address translation mechanism using a hardware-accessed segment table in main storage. (For more information, see Section 9.2, “Segment Lookaside Buffer Management”.)

 To enhance performance of virtual-to-real conversions, most implementations provide a translation lookaside buffer (TLB). The TLB is, basically, a special cache for keeping the recently used page table entries (PTEs). The format and size of the page table is defined by the Power ISA. The TLB need not be kept consistent with the hardware-accessed page table in main storage. Coherency of the TLB is maintained by system software using instructions provided by the Power ISA. All implementations must support a virtual-to-real-address translation mechanism using a hardware-accessed page table in main storage.


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