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 9.1. Storage Segment Table

 In the Power Architecture, the storage segments are loaded directly into the processor's SLB using the slbmte instruction. For a CAIA-compliant accelerator, the PSL searches for a storage segment in a segment table located in system memory. The virtual address pointer to the storage segment table is defined by the concatenation of the values in the Storage Segment Table Pointer Zero Register (SSTP0_An) and Storage Segment Table Pointer One Register (SSTP1_An).

 The storage segment table is a variable sized (256 B - 1 MB) structure located in main storage. The table must be naturally aligned to the size of the table, and the storage must be mapped as not caching inhibited and memory coherency required (that is a storage control setting of WIMG = '0010'). The real memory for the segment table must be contiguous and mapped by a single page-table entry (PTE).

 Each storage segment table entry (SSTE) maps one effective segment to one virtual segment. Table 9.1, “Storage Segment Table Entry ” shows the format of an entry in the storage segment table. See the Power ISA, Book III for a definition of each field in the SSTE.

 

Table 9.1. Storage Segment Table Entry

Storage Segment Table Entry

0 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

 Upper bits of ESID

 ESID (LSbs)

 V

 Reserved

 B

 Upper bits of VSID

 Lower bits of VSID

 Ks

 Kp

 N

 L

 C

  Rsv

 LP

 Reserved


 

Figure 9.1. Storage Segment Table



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