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 Chapter 8. Interrupts

 The PSL uses the PCIe message signaled interrupt (MSI-X) mechanism for the presentation of all interrupts. The MSI-X address and data are calculated by the PSL from values in the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers or the corresponding process element entries. There are three modes for calculating the address and data: fixed platform-specific address, single MSI-X table entry, and full MSI-X table. The mode supported by the PSL is provided in the status field (bit 14:13) of the vendor-specific extended configuration capability (VSEC) structure.

 When operating with a fixed platform-specific address or a single MSI-X table entry, the PSL posts an interrupt using a PCIe posted write operation to address (MSI-X_Base_Addr | (x'00000000000' || IVTE || x'0') with data (x'0000000000000000'); where the IVTE value is calculated using the equation in Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)”. The MSI-X_Base_Address is either a fixed 64-bit platform-specific value or the 64-bit MSI-X address at entry 0 of the MSI-X table. By performing this operation, the IVTE value directly indexes into an interrupt vector table stored in system memory. The data for the MSI-X operation is always zero. In this mode, the pending bit array (PBA) is not used.

 When operating with a full MSI-X table, MSI-X interrupts are presented to the system using a posted write with an address and data specified from an MSI-X table. For a CAIA-compliant device, the index into the MSI-X table to select the address and data is the IVTE. The IVTE is calculated using the equation in Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)”. In this mode, the pending bit array is also used.

[Note]Note

 In a POWER system, an MSI-X interrupt is presented using a 64-bit address of x'10000000000vvvv0'. The 16-bit value represented by 'v' is the interrupt vector table entry (IVTEn). For the single MSI-X entry mode, entry 0 provides a means of setting the base address.

 The PSL can present a programmable number of interrupts (n) per context (process element) and one error interrupt. The logical interrupt source number (LISNn) presented to the PSL by the AFU is converted into a 16-bit interrupt vector table entry (IVTE) offset using the PSL_IVTE_Offset_An and the PSL_IVTE_Limit_An Registers. (See Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)” for the mapping of an LISN to an IVTE.) The error interrupt is provided in the PSL_ErrIVTE Register. The PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers are either loaded from the process element in the shared virtualization programming models, or set using MMIO by the hypervisor in the dedicated-process programming model.

 The PSL posts an interrupt using a PCIe posted write operation to address (x'1000000000000000' | (x'00000000000' || IVTE || x'0') with data (x'0000000000000000'); where the IVTE value is calculated using the equation in Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)”. By performing this operation, the IVTE value directly indexes into an interrupt vector table stored in system memory.

 For more information on the interrupt vector table and how interrupts are processed by the POWER processor, see the I/O Design Architecture v2 Specification for the Power Architecture platform.


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