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 B.3. Interrupt Examples

 In the PCIe architecture, MSI-X interrupts are presented to the host processor using a PCIe posted write operation. The address and data for the posted write operation are programmable using a MSI-X table in the MMIO space. The CAIA supports three modes for selecting the address and data for the MSI-X interrupt: fixed platform-specific address, single MSI-X table entry, and full MSI-X table.

 Interrupts in the CAIA are presented to the host processor using a mechanism layered on top of the PCIe MSI-X interrupts. The main difference between the PCIe architecture and CAIA for interrupts is the source of the address and data for the posted write operation.

 For a CAIA-compliant device operating with a fixed platform-specific address or a single MSI-X entry, the address is calculated using the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers, and the address provided in entry zero of the MSI-X table. The data is always zero for this mode. The PSL_IVTE_Offset_An and PSL_IVTE_An Registers are either set directly using an MMIO in a dedicated-process model or sourced from the process element in a virtualization model. The following equations are used to generate the address for the PCIe posted write operation from the AFU LISNs.

 Note: For PSL interrupts reported in the PSL_DSISR_An Register, the LISN is always zero. For PSL error interrupts, the IVTE is sourced directly from the PSL_ErrIVTE Register. The AFU_LISN must be between the range 1 AFU_LISN (Max_Ints - 1). The maximum number of interrupts (Max_Ints) is the sum of the interrupt ranges (PSL_IVTE_Limit_An[IVTE_Range_x]).

IVTE = PSL_IVTE_Offset_An[IVTE_Offset_0] + AFU_LISN;
         when (1 <= AFU_LISN < PSL_IVTE_Limit_An[IVTE_Range_0]) 
         AND (PSL_IVTE_Limit_An[IVTE_Range_0] != 0)
       else

IVTE = PSL_IVTE_Offset_An[IVTE_Offset_1] + (AFU_LISN - 
                                            PSL_IVTE_Limit_An[IVTE_Range_0]); 
         when ( (PSL_IVTE_Limit_An[IVTE_Range_0])
              <= AFU_LISN < 
                 (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1]) ) 
         AND (PSL_IVTE_Limit_An[IVTE_Range_1] != 0)
       else

IVTE = PSL_IVTE_Offset_An[IVTE_Offset_2] + ( AFU_LISN -
       (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1]) ); 
          when ( (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1])
               <= AFU_LISN < 
                 (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1] +
                  PSL_IVTE_Limit_An[IVTE_Range_2]) )
          AND (PSL_IVTE_Limit_An[IVTE_Range_2] != 0)
       else

IVTE = PSL_IVTE_Offset_An[IVTE_Offset_3] + ( AFU_LISN -
       (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1] +
        PSL_IVTE_Limit_An[IVTE_Range_2]) );
         when ( (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1] +
                 PSL_IVTE_Limit_An[IVTE_Range_2])
              <= AFU_LISN < 
                 (PSL_IVTE_Limit_An[IVTE_Range_0] + PSL_IVTE_Limit_An[IVTE_Range_1] +
                  PSL_IVTE_Limit_An[IVTE_Range_2] + PSL_IVTE_Limit_An[IVTE_Range_3]) ) 
         AND (PSL_IVTE_Limit_An[IVTE_Range_3] != 0)
       else

No IVTE is generated and No Interrupt is sent for the AFU.

Single MSI-X Table Entry:
   PCIe_MSI-X_address = (MSI-X_Base | (x'00000000000' || IVTE || x'0')
   PCIe_MSI-X_data = 0
         where the MSI-X_Base is either x'1000000000000000' for platform specific 
         fixed address or the address from MSI-X_Table_entry[0].

Full MSI-X Table:
   PCIe_MSI-X_address = MSI-X_Table_entry[IVTE]
   PCIe_MSI-X_data = MSI-X_Table_entry[IVTE]


  • Note: For POWER Systems, the MSI-X_Base is x'1000000000000000'. System software should set the address in entry zero of the MSI-X table to the base address for MSI-X interrupts.

 Note: For PSL interrupts reported in the PSL_DSISR_An Register, the IVTE is PSL_IVTE_Offset_An[IVTE_Offset_0] (an LISN of zero). For PSL error interrupts, the IVTE is sourced directly from the PSL_ErrIVTE Register. The AFU_LISN must be between the range 1 AFU_LISN < (Max_Ints - 1). The maximum number of interrupts (Max_Ints) is the sum of the interrupt ranges (PSL_IVTE_Limit_An[IVTE_Range_x]).

 The MSI-X address is used by the POWER processor to create an interrupt source number (ISN) and an offset into an interrupt vector table (IVT_Offset). The IVT_Offset selects an interrupt vector table entry (IVTE) located in system memory that contains the interrupt priority and the destination server number. The destination server number defines the destination server or group of servers that should handle the interrupt. The equations for generating the ISN and the IVT_Offset are as follows:

IVT_Offset = (PCIe_MSI-X_address[44..63] | (IVTE || x'0') ); for big endian numbering 
             (PCIe_MSI-X_address[19..0] | (IVTE || x'0') ); for little endian numbering
ISN =        PCIe_MSI-X_address[44..59] (big endian numbering) 
             PCIe_MSI-X_address[19..4] (little endian numbering)

 In a POWER system, the interrupt vector table (IVT) in memory can be a maximum of 220 bytes in length with each entry being 16 bytes (or 216 total entries). The PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers provide the hypervisor with a mechanism for limiting an operating system to a range of entries in the IVT.


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