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 Appendix C. Glossary

AFE

Accelerator function environment.

 AFU

 Accelerator function unit.

 architecture

 A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations.

 AUI

 Accelerator unit interface.

 big endian

 A byte-ordering method in memory where the address n of a word corresponds to the most-significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte. See little endian.

 cache

 High-speed memory close to a processor. A cache usually contains recently-accessed data or instructions, but certain cache-control instructions can lock, evict, or otherwise modify the caching of data or instructions.

 caching inhibited

 A memory update policy in which the cache is bypassed, and the load or store is performed to or from system memory.

 A page of storage is considered caching inhibited when the 'I’ bit has a value of '1’ in the page table. Data located in caching inhibited pages cannot be cached at any memory hierarchy that is not visible to all processors and devices in the system. Stores must update the memory hierarchy to a level that is visible to all processors and devices in the system.

 CAIA

 Coherent Accelerator Interface Architecture.

 Defines an architecture for loosely coupled coherent accelerators. The Coherent Accelerator Interface Architecture provides a basis for the development of accelerators coherently connected to a POWER processor.

 CAPI

 Coherent Accelerator Processor Interface.

 coherence

 Refers to memory and cache coherence. The correct ordering of stores to a memory address, and the enforcement of any required cache write-backs during accesses to that memory address. Cache coherence is implemented by a hardware snoop (or inquire) method, which compares the memory addresses of a load request with all cached copies of the data at that address. If a cache contains a modified copy of the requested data, the modified data is written back to memory before the pending load request is serviced.

 CRC

 Cyclic redundancy check.

 DAR

 Data Address Register.

 DMA

 Direct memory access. A technique for using a special-purpose controller to generate the source and destination addresses for a memory or I/O transfer.

 EA

 Effective address.

 An address generated or used by a program to reference memory. A memory-management unit translates an effective address to a virtual address, which it then translates to a real address (RA) that accesses real (physical) memory. The maximum size of the effective-address space is 264 bytes.

 ECC

 Error correction code.

 A code appended to a data block that can detect and correct bit errors within the block.

 ERAT

 Effective-to-real-address translation, or a buffer or table that contains such translations, or a table entry that contains such a translation.

 ESID

 Effective segment ID.

 exception

 An error, unusual condition, or external signal that can alter a status bit and will cause a corresponding interrupt, if the interrupt is enabled. See interrupt.

 fetch

 Retrieving instructions from either the cache or system memory and placing them into the instruction queue.

 guarded

 Prevented from responding to speculative loads and instruction fetches. The operating system typically implements guarding, for example, on all I/O devices.

 HAUR

 Hypervisor accelerator utilization record.

 HCA

 Hot/cold assist.

 hypervisor

 A control (or virtualization) layer between hardware and the operating system. It allocates resources, reserves resources, and protects resources among (for example) sets of AFUs that might be running under different operating systems.

 implementation

 A particular processor that conforms to the architecture but might differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features.

 INT

 Interrupt.

 A change in machine state in response to an exception.

 ISA

 Instruction set architecture.

 ISN

 Interrupt source number.

 IVT

 Interrupt vector table.

 IVTE

 Interrupt vector table entry.

 KB

 Kilobyte.

 LA

 A local storage (LS) address of a PSL list. It is used as a parameter in a PSL command.

 LISN

 Logical interrupt source number.

 little endian

 A byte-ordering method in memory where the address n of a word corresponds to the least-significant byte. In an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte. See big endian.

 LISN

 Logical interrupt source number.

 LPAR

 Logical partitioning.

 A function of an operating system that enables the creation of logical partitions.

 LPC

 Lowest point of coherency.

 LPID

 logical-partition identity.

 LSb

 Least-significant bit.

 The bit of least value in an address, register, data element, or instruction encoding.

 main storage

 The effective-address space. It consists physically of real memory (whatever is external to the memory-interface controller), local storage, memory-mapped registers and arrays, memory-mapped I/O devices, and pages of virtual memory that reside on disk. It does not include caches or execution-unit register files.

 mask

 A pattern of bits used to accept or reject bit patterns in another set of data. Hardware interrupts are enabled and disabled by setting or clearing a string of bits, with each interrupt assigned a bit position in a mask register.

 MB

 Megabyte.

 memory coherency

 An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory.

 memory mapped

 Mapped into the Coherent Attached Accelerator’s addressable-memory space. Registers, local storage (LS), I/O devices, and other readable or writable storage can be memory-mapped. System software does the mapping.

 MMIO

 Memory-mapped input/output. See memory mapped.

 MMU

 Memory management unit. A functional unit that translates between effective addresses (EAs) used by programs and real addresses (RAs) used by physical memory. The MMU also provides protection mechanisms and other functions.

 MSb

 Most-significant bit.

 The highest-order bit in an address, registers, data element, or instruction encoding.

 MSI

 Message signaled interrupt.

 MSR

 Machine State Register.

 no-op

 No-operation. A single-cycle operation that does not affect registers or generate bus activity.

 OS

 Operating system.

 page

 A region in memory. The Power Architecture defines a page as a 4 KB area of memory, aligned on a 4 KB boundary or a large page size that is implementation dependent.

 PBA

 Pending bit array.

 PBT

 Push block transfer.

 PCE

 PCIe® Configuration Environment.

 PCIe®

 Peripheral Component Interface Express.

 PEAM

 Process element authority mask.

 POR

 Power-on reset.

 POWER

 Of or relating to the Power ISA or the microprocessors that implement this architecture.

 Power ISA

 A computer architecture that is based on the third generation of reduced instruction set computer (RISC) processors.

 privileged mode

 Also known as supervisor mode. The permission level of operating system instructions. The instructions are described in PowerPC Architecture, Book III and are required of software that accesses system-critical resources.

 problem state

 The permission level of user instructions. The instructions are described in Power ISA, Books I and II and are required of software that implements application programs.

 PSL

 POWER Service Layer.

 It is the interface logic for a coherently attached accelerator and provides two main functions: moves data between accelerator function units (AFUs) and main storage, and synchronizes the transfers with the rest of the processing units in the system.

 PTE

 Page table entry.

 A table that maps virtual addresses (VAs) to real addresses (RAs) and contains related protection parameters and other information about memory locations.

 RA

 Real address.

 An address for physical storage, which includes physical memory, local storage (LS), and memory mapped I/O registers. The maximum size of the real-address space is 262 bytes.

 ROM

 Read-only memory.

 SLB

 Segment lookaside buffer. It is used to map an effective address to a virtual address.

 slbia

 SLB invalidate all instruction.

 slbie

 SLB invalidate entry instruction.

 slbmte

 SLB move to entry instruction.

 SSE

 System software environment.

 SST

 Storage segment table.

 STABORG

 Segment table origin.

 STE

 Segment table entry.

 storage model

 A CAIA-compliant accelerator implements a storage model consistent with the Power ISA.

 sync

 Synchronize instruction.

 synchronization

 The process of arranging storage operations to complete in the order of occurrence.

 system software

 Software that has access to the privileged modes of the architecture. System software is a reference to hypervisor and operating system software.

 TAG

 PSL command tag.

 tag group

 A group of PSL commands. Each PSL command is tagged with an n-bit tag group identifier. An AFU can use this identifier to check or wait on the completion of all queued commands in one or more tag groups.

 TLB

 Translation lookaside buffer. An on-chip cache that translates virtual addresses (VAs) to real addresses (RAs). A TLB caches page-table entries for the most recently accessed pages, thereby eliminating the necessity to access the page table from memory during load-store operations.

 tlbie

 Translation lookaside buffer invalidate entry instruction.

 VA

 Virtual address. An address to the virtual-memory space, which is typically much larger than the real address space and includes pages stored on disk. It is translated from an effective address by a segmentation mechanism and used by the paging mechanism to obtain the real address (RA). The maximum size of the virtual-address space is 265 bytes.

 VPD

 Vital product data.

 VPN

 Virtual page number. The number of the page in virtual memory.

 VSEC

 Vendor-Specific Extended Configuration Capability

 VSID

 Virtual segment ID.

 WIMG bits

 Four bits in the page table, also called a page-table entry, which control the processor's accesses to cache and main storage. 'W’ stands for write through, 'I’ for cache inhibit, 'M’ for memory coherence, and 'G’ for guarded storage.

 word

 Four bytes.


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