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 Appendix A. Memory Maps 

 This appendix contains the mapping of all registers defined by the Coherent Accelerator Interface Architecture (CAIA) in the real address space. As shown in Table A.1, “CAIA-Compliant Processor Memory Map”, the memory map for a single CAIA-compliant processor is divided into five sections:

 The starting location for the memory map is defined in implementation-dependent base address registers (P1_Base and P2_Base). The base registers are used to calculate the address for all registers. An implementation can place address holes in the memory map (that is, areas where registers are not defined) to simplify decoding of the registers. The base registers for a CAIA-compliant accelerator are implementation dependent. See the specific implementation documentation for more information.

[Note] Implementation Note:

 A CAIA-compliant accelerator implementation must provide at least two base registers for relocating the internal registers. All base register (P1_Base and P2_Base) values must be initialized during the PCIe initialization sequence. The base registers are set using the standard PCIe BAR registers.

A CAIA-compliant accelerator must respond to the full address range specified by the base registers and the implementation-dependent memory map. An implementation must respond to all address holes. A value of zero must be returned for all read operations, and the data is ignored for all write operations.

 

Table A.1. CAIA-Compliant Processor Memory Map

Real Address (Hexadecimal)

Area

Description

Privilege 1 (P1) Area for PSL

  • This area should be mapped with a WIMG setting of '0101'.

 P1_Base

 Start of P1 area

 Start of the privilege 1 area

 P1_Base + x'FFFF'

 End of P1 area

 End of the privilege 1 area

Privilege 1 for each PSL slice (P1(n)) Area; where 0 ≤ n ≤ (maximum number of PSL slices - 1)[a]

  • P1(0) ≥ x'10000': The starting address of the area.

  • P1(n) = P1(0) + (n + x'100'); where 0 ≤ n ≤ (maximum number of PSL slices - 1).[a]

  • This area should be mapped with a WIMG setting of '0101'.

 P1_Base | P1(n)

 Start of P1(n) area

 Start of the privilege 1 area for PSL_Slice(n)

 P1_Base | (P1(n) + x'FF')

 End of P1(n) area

 End of the privilege 1 area for PSL_Slice(n)

  PSL  Privilege 2 (P2(n)) Area; where 0 ≤ n ≤ (maximum number of PSL slices - 1)[a]

  • P2(n) = (n × x'1000'); where 0 ≤ n ≤ (maximum number of PSL slices- 1).[a]

  • This area should be mapped with a WIMG setting of '0101'.

 P2_Base |  P2(n)

 Start of P2(n) area

 Start of the privilege 2 area for PSL_Slice(n)

 P2_Base | (P2(n) + x'FFFF')

 End of P2(n) area

 End of the privilege 2 area for PSL_Slice(n)

AFU Descriptor (AD(n)) Area; where 0 ≤ n ≤ (maximum number of AFUs - 1)[a]

  • AD(0) ≥ P2(max) + X'10000'; where max = (maximum number of PSL Slices - 1).[b]

  • AD(n) = PS(0) + (n × AD_Size[c] ); where 0 ≤ n ≤ (maximum number of AFUs - 1)[a].

  • This WIMG settings for this area is AFU implementation specific. The typical WIMG setting is '0101'.

 P2_Base | AD(n)

 Start of PS(n) area

 Start of the problem state area for AFU(n)

 P2_Base | (AD(n) + AD_Size[c] - 1)

 End of PS(n) area

 End of the problem state area for AFU(n)

AFU Problem State (PS(n)) Area; where 0 ≤ n ≤ (maximum number of AFUs - 1)[a]

  • PS(0) ≥ AD(max) + (AD_Size[c] × n); where 0 ≤ n ≤ (maximum number of AFUs - 1)[a] , max = (maximum number of PSL Slices - 1).[b]

  • PS(n) = PS(0) + (n × PS_Size[d] ); where 0 ≤ n ≤ (maximum number of AFUs - 1).[a]

  • This WIMG settings for this area are AFU implementation specific. The typical WIMG setting is '0101'. Some implementations might support regions of this area to be mapped as not guarded (G = 0) to allow store gathering for better performance.

 P2_Base | PS(n)

 Start of PS(n) area

 Start of the problem state area for AFU(n)

 P2_Base | (PS(n) + PS_Size[d] - 1)

 End of PS(n) area

 End of the problem state area for AFU(n)

Note: This table assumes that the base starts on a power of 2 boundary that is greater than or equal to the size of the memory map area.

[a] The value n ranges from zero to the number of PSL slices or AFUs minus 1 (0 ≤ n ≤ maximum number of AFUs -1). If the number of AFUs is not a power of 2, an implementation can choose to increase the value of n to the next power of 2 boundary and reserve the extra space. Doing so simplifies decoding the address ranges. There is one PSL_Slice for each AFU.

[b] The problem state area for AFU 0 starts at the next natural boundary for the problem state area reserved for a single AFU slice. For example, the problem state area for a single AFU design with 32 MB of area reserved starts on the next 32 MB boundary from the privileged 2 base.

[c] The AFU descriptor size (AD_Size) is an implementation-dependent parameter. The AFU descriptor size is provided in the Vendor Specific Extended Configuration (VSEC). PSL implementations must consider reserving 64 KB (0x100000) of space for each AFU descriptor. For more information, see the implementation-specific documentation and Section 12.3, “CAIA Vendor-Specific Extended Capability Structure”.

[d] The problem state area size (PS_Size) is an implementation-dependent parameter. PSL implementations must consider reserving 32 MB (x'2000000') of space for CAPI devices using on-adapter memory. For more information, see the implementation-specific documentation.



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