Revision history   OpenPOWER Library

 A.3. PSL Slice Privilege 2 Memory Map

 Table A.4, “PSL Slice Privilege 2 Memory Map” lists all the CAIA-compliant PSL slice registers that allow only privilege 2 access.

  

 

Table A.4. PSL Slice Privilege 2 Memory Map

Offset (Hexadecimal)

Register

Description

Access Type

 Configuration and Control Area

  x'0000'

 PSL_PID_TID_An

 Section 10.2.1, “PSL Process and Thread Identification Register(PSL_PID_TID_An)” for AFU n

 Read/Write

  x'0008'

 CSRP_An

 Section 10.2.2, “Context Save/Restore Pointer Register(CSRP_An)” for AFU n[a]

 Read/Write

 x'0010'

 AURP0_An

 Section 10.2.3.1, “Accelerator Utilization Record Pointer Zero Register (AURP0_An)” for AFU n[a]

 Read/Write

 x'0018'

 AURP1_An

 Section 10.2.3.2, “Accelerator Utilization Record Pointer One Register (AURP1_An)” for AFU n[a]

 Read/Write

 x'0020'

 SSTP0_An

 Section 10.2.4.1, “Storage Segment Table Pointer Zero Register (SSTP0_An)” for AFU n

 Read/Write

 x'0028'

 SSTP1_An

 Section 10.2.4.2, “Storage Segment Table Pointer One Register (SSTP1_An)” for AFU n

 Read/Write

  x'0030'

 PSL_AMR_An

 Section 10.2.5, “PSL Authority Mask Register(PSL_AMR_An) ” for AFU n

 Also see the PowerPC Architecture, Book III for a description of this register.

 Read/Write

 x'0038'

 Reserved

 Reserved

 Reserved

 Segment Lookaside Buffer Management Registers

  x'0040'

 SLBIE_An

 Section 10.2.6.1, “SLB Invalidate Entry Register (SLBIE_An)” For AFU n

 Effective segment ID (ESID) of the SLB entry to invalidate.

 Read/Write

  x'0048'

 SLBIA_An

 Section 10.2.6.2, “SLB Invalidate All Register (SLBIA_An)” For AFU n

 Invalidate all SLB entries.

 Read/Write

  x'0050'

 SLBI_Select_An

 Section 10.2.6.2, “SLB Invalidate All Register (SLBIA_An)” For AFU n

 Lookaside buffer invalidate selector.

 Read/Write

 x'0058' - x'005F'

 Reserved

 Reserved

 Reserved

 Interrupt Registers

  x'0060'

 PSL_DSISR_An

 Section 10.2.7, “PSL Data Storage Interrupt Status Register(PSL_DSISR_An)” for AFU n Also see the PowerPC Architecture, Book III for a description of this register.

 Read Only

  x'0068'

 PSL_DAR_An

 Section 10.2.8, “PSL Data Address Register (PSL_DAR_An)” for AFU n

 Also see the PowerPC Architecture, Book III for a description of this register.

 Read Only

  x'0070'

 PSL_DSR_An

 Section 10.2.9, “PSL Data Segment Register (PSL_DSR_An)” for AFU n

 Also see the PowerPC Architecture, Book III for a description of the fields in this register.

 Read Only

  x'0078'

 PSL_TFC_An

 Section 10.2.10, “PSL Translation Fault Control Register (PSL_TFC_An)” for AFU n

 Read/Write

  x'0080'

 PSL_PEHandle_An

 Section 10.2.11, “PSL Process Element Handle Register (PSL_PEHandle_An)” for AFU n[a]

 Read Only

  x'0088'

 PSL_ErrStat_An

 Section 10.2.12, “PSL Error Status Register (PSL_ErrStat_An)” for AFU n

 Read/Write

 AFU Registers

  x'0090'

 AFU_Cntl_An

 Section 10.2.13, “AFU Control Register (AFU_Cntl_An)” for AFU n

 Read/Write

  x'0098'

 AFU_ERR_An

 Section 10.2.14, “AFU Error Register (AFU_ERR_An)” for AFU n

 Read Only

 Work Element Descriptor

  x'00A0'

 PSL_WED_An

 Section 10.2.15, “PSL WED Register(PSL_WED_An)” for AFU n

 Read/Write

 x'00A8' - x'00BF'

 Reserved

 Reserved

 Reserved

 Reserved

 x'00C0' - x'00FF'

 Reserved

 Reserved

 Reserved

 Implementation-Dependent Area. (See the specific implementation documentation for a detailed description of these registers.)

  x'0100' - x'FFFF'

    PV2_ImplRegs

 Privilege 2 implementation-dependent registers

  

[a] Implementation of this facility is optional. 



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