Revision history   OpenPOWER Library

 A.2. PSL Slice Privilege 1 Memory Map

 Table A.3, “PSL Slice Privilege 1 Memory Map ” lists all the CAIA-compliant PSL slice registers that allow only privilege 1 access.

  

 

Table A.3. PSL Slice Privilege 1 Memory Map

Offset (Hexadecimal)

Register

Description

Access Type

 Configuration Area

  x'00'

 PSL_SR_An

 Section 10.1.1, “PSL State Register (PSL_SR_An)” for AFU n

 Read/Write

  x'08'

 PSL_LPID_An

 Section 10.1.2, “PSL Logical Partition ID Register (PSL_LPID_An)” for AFU n

 Read/Write

  x'10'

 PSL_AMBAR_An

 Section 10.1.3, “PSL AFU Memory Base Address Register (PSL_AMBAR_An)” for AFU n[a]

 Read/Write

  x'18'

 PSL_SPOffset_An

 Section 10.1.4, “PSL AFU Scratch Pad Offset Register (PSL_SPOffset_An)” for AFU n[a]

 Read/Write

  x'20'

 PSL_ID_An

 Section 10.1.5, “PSL ID Register (PSL_ID_An)” for AFU n

 Read/Write

  x'28'

 PSL_SERR_An

 Section 10.1.6, “PSL Slice Error Register (PSL_SERR_An)” for AFU n

 Read/Write

 Memory Management Registers

  x'30'

 PSL_SDR_An

 Section 10.1.7, “PSL Storage Description Register (PSL_SDR_An)” for AFU n

 Also see the PowerPC Architecture, Book III for a description of this register.

 Read/Write

  x'38'

 PSL_AMOR_An

 Section 10.1.8, “PSL Authority Mask Override Register (PSL_AMOR_An)” for AFU n

 Also see the PowerPC Architecture, Book III for a description of this register.

 Read/Write

 x'40' - x'5F'

 Reserved

 Reserved

 Pointer Area

  x'80'

 HAURP_An

 Section 10.1.9, “Hypervisor Accelerator Utilization Record Pointer Register (HAURP_An)” for AFU n[a]

 Read/Write

  x'88'

 PSL_SPAP_An

 Section 10.1.10, “PSL Scheduled Processes Area Pointer Register (PSL_SPAP_An)” for AFU n[a]

 Read/Write

  x'90'

 PSL_LLCMD_An

 Section 10.1.11, “PSL Linked List Command Register (PSL_LLCMD_An)” for AFU n[a]

 Read/Write

 x'98' - x'9F'

 Reserved

 Reserved

 Control Area

  x'A0'

 PSL_SCNTL_An

 Section 10.1.12, “PSL Slice Control Register (PSL_SCNTL_An)” for AFU n

 Read/Write

  x'A8'

 PSL_CtxTime_An

 Section 10.1.13, “PSL Context Swap Time Slice Register(PSL_CtxTime_An)”[a]

 Read/Write

  x'B0'

 PSL_IVTE_Offset_An

 Section 10.1.14, “PSL IVTE Offset Register (PSL_IVTE_Offset_An)” for AFU n

 Read/Write

  x'B8'

 PSL_IVTE_Limit_An

 Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)” for AFU n

 Read/Write

 Implementation-Dependent Area. (See the specific implementation documentation for a detailed description of these registers).

  x'C0' - x'FF'

    PV1n_ImplRegs

 Privilege 1 implementation-dependent registers

  

[a] Implementation of this facility is optional.



loading table of contents...