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 A.1. PSL Privilege 1 Memory Map

 Table A.2, “PSL Privilege 1 Memory Map” lists all the CAIA-compliant PSL registers that allow only privilege 1 access.

  

 

Table A.2. PSL Privilege 1 Memory Map

Offset (Hexadecimal)

Register

Description

Access Type

 Configuration and Control Area

  x'0000'

 PSL_CtxTime

 Section 10.1.16, “PSL Context Swap Time Register (PSL_CtxTime)”[a]

 Read/Write

  x'0008'

 PSL_ErrIVTE

 Section 10.1.17, “PSL Error Interrupt Register (PSL_ErrIVTE)”

 Read/Write

  x'0010'

 PSL_KEY1

 Section 10.1.18, “PSL Key One Register (PSL_KEY1)”

 Write

  x'0018'

 PSL_KEY2

 Section 10.1.20, “PSL Control Register (PSL_Control)”

 Write

  x'0020'

 PSL_Control

 Section 10.1.20, “PSL Control Register (PSL_Control)”

 Write

 x'0028' - x'005F'

 Reserved

 Reserved

 AFU Download Control

  x'0060'

 AFU_DLCNTL

 Section 10.1.21, “AFU Download Control Register (AFU_DLCNTL)”[a]

 Read/Write

  x'0068'

 AFU_DLADDR

 Section 10.1.22, “AFU Download Address Register (AFU_DLADDR)”[a]

 Read/Write

 x'0070' - x'007F'

 Reserved

 Reserved

 PSL Lookaside Buffer Management Area

  x'0080'

 PSL_LBISEL

 Section 10.1.1, “PSL State Register (PSL_SR_An)”

 PID and LPID of the translations to invalidate.

 Read/Write

  x'0088'

 PSL_SLBIE

 Section 10.1.24, “PSL SLB Invalidate Entry Register (PSL_SLBIE) ”

 Effective segment ID (ESID) of the SLB entry to invalidate.

 Read/Write

  x'0090'

 PSL_SLBIA

 Section 10.1.25, “PSL SLB Invalidate All Register (PSL_SLBIA)”

 Invalidate all SLB entries.

 Read/Write

 x'0098'

 Reserved

 Reserved

  x'00A0'

 PSL_TLBIE

 Section 10.1.26, “PSL TLB Invalidate Entry (PSL_TLBIE)”

 Virtual address (VA) of the TLB entry to invalidate.

 Read/Write

  x'00A8'

 PSL_TLBIA

 Section 10.1.27, “PSL TLB Invalidate All (PSL_TLBIA)”

 Invalidate all TLB entries.

 Read/Write

  x'00B0'

 PSL_AFUSEL

 Section 10.1.28, “PSL AFU Selection Register (PSL_AFUSEL)”

 AFU slice selection for the translations to invalidate.

 Read/Write

 x'00B8' - x'00BF'

 Reserved

 Reserved

 Implementation-Dependent Area. (See the specific implementation documentation for a detailed description of these registers).

 x'00C0' - x'7EFF'

    PV1_ImplRegs

 Privilege 1 implementation-dependent registers

  

 PCIe MSI-X Pending Bit Array (PBS) Area. (Not used. Reserved for future compatibility with PCIe MSI-X Architecture).

 x'7F00' - x'7FFF'

    MSI-X_PBA

 Reserved area for MSI-X pending bit array (PBA). The PCIe MSI-X extended capability structure points to the start of this location for the pending bit array. This area is not used by the PSL but must be reserved for compatibility with the PCIe standard.

 One bit per MSI-X table entry (maximum 2048 bits).

  

 PCIe MSI-X Table Area. (Not used. Reserved for future compatibility with PCIe MSI-X Architecture).

 x'8000' - x'FFFF'

    MSI-X_Table

 Reserved area for the MSI-X Table. The PCIe MSI-X extended capability structure points to the start of this location for the MSI-X table. This area is not used by the PSL but must be reserved for compatibility with the PCIe standard.

MSI-X table entry consist of (maximum 2048 entries):Word 2 = Interrupt data
Word 0 = Lower 32-bits of interrupt message addressWord 3 = Interrupt vector control
Word 1 = Upper 32-bits of interrupt message address 
 

[a] Implementation of this facility is optional.



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