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 A.4. AFU Descriptor Memory Map

 Table A.5, “AFU Descriptor Memory Map” lists all the required AFU descriptor registers for a CAIA-compliant device.

  

 

Table A.5. AFU Descriptor Memory Map

Offset (Hexadecimal)

Register

Description

Access Type

 AFU Descriptor Header

 x'0'

 num_ints_per_process

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 x'2'

 num_of_processes

 Read/Write

 x'4'

 num_of_afu_CRs

 Read Only

 x'6'

 req_prog_model

 Read Only

 x'8' - x'1F'

 Reserved

 Reserved

 Reserved

 AFU Configuration Record Header

 x'20'

 AFU_CR_len

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 Read Only

 x'22' - x'27'

 Reserved

 Reserved

 Reserved

 x'28'

 AFU_CR_offset

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 AFU Problem State Area Control

 x'30'

 PerProcessPSA_control

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 x'31'

 PerProcessPSA_length

 Read Only

 x'38'

 PerProcessPSA_offset

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 AFU Error Buffer

 x'40'

 AFU_EB_len

 Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read Only

 x'48'

 AFU_EB_offset

  

 Read Only

 AFU Configuration Record Area

 AFU_CR_offset

 AFU_CR_Area_Start

 Start of AFU Configuration Record area. See Section 11.1, “AFU Descriptor Format” for AFU n[a]

 Read/Write

 AFU_CR_offset +

 (num_of_afu_CRs * AFU_CR_len) - 1

 AFU_CR_Area_End

[a] All accesses to these registers must be either 32-bit or 64-bit operations.



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