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 Chapter 3. Introduction to Coherent Accelerator Interface Architecture

 The  Coherent Accelerator Interface Architecture (CAIA) defines an accelerator interface structure for coherently attaching accelerators to the IBM Power Systems™ using a standard PCIe bus. The intent is to allow implementation of a wide range of accelerators to optimally address many different market segments.

 The CAIA allows a single PSL to support multiple AFUs. Architecturally, the only limit on the number of AFUs is the amount of address space assigned to the PSL. The PSL manages the context and virtual addressing for each AFU. While there is only one physical PSL on each physical CAIA-compliant device, some registers in the PSL are duplicated for each AFU, which essentially provides a "virtual"; PSL for each AFU. Providing this virtual PSL allows software to treat each AFU independently.

 The CAIA document covers three main areas: the POWER Service Layer (PSL), the accelerator function unit (AFU) interface, and the PCIe configuration environment. The PSL section covers the facilities and procedures provided to system software (hypervisor and operating systems) for managing a CAIA-compliant device. The AFU interface section describes the interface facilities available to an accelerator function. The PCIe configuration environment covers the architecture for the configuration space when a CAIA-compliant device is connected using a PCIe bus.

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