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 3.5. Conformance to the CAIA

 Any implementation of this architecture must adhere to the following set of numbered conformance clauses to claim conformance to CAIA:

  1.  Must implement at least one of the specified programming models.

  2.  Must implement the required facilities defined in this specification.

  3.  Optionally, may implement optional categories defined in this specification.

 

 

Table 3.2. CAIA Conformance

Register Name

Required/Optional

 Per AFU Slice Facilities (Privilege 1)

 PSL State Register (PSL_SR_An)

 Required

 PSL Logical Partition ID Register (PSL_LPID_An)

 Required

 PSL AFU Memory Base Address Register (PSL_AMBAR_An)

 Optional

 PSL AFU Scratch Pad Offset Register (PSL_SPOffset_An)

 Optional

 PSL ID Register (PSL_ID_An)

 Required

 PSL Slice Error Register (PSL_SERR_An)

 Optional

 PSL Storage Description Register (PSL_SDR_An)

 Required

 PSL Authority Mask Override Register (PSL_AMOR_An)

 Required

 Hypervisor Accelerator Utilization Record Pointer Register (HAURP_An)

 Optional

 PSL Scheduled Processes Area Pointer Register (PSL_SPAP_An)

 Required

 PSL Linked List Command Register (PSL_LLCMD_An)

 Optional

 PSL Slice Control Register (PSL_SCNTL_An)

 Required

 PSL Context Swap Time Slice Register(PSL_CtxTime_An)

 Optional

 PSL IVTE Offset Register (PSL_IVTE_Offset_An)

 Required

 PSL IVTE Limit Register (PSL_IVTE_Limit_An)

 Required

 PSL Facilities (Privilege 1)

 PSL Context Swap Time Register (PSL_CtxTime)

 Optional

 PSL Error Interrupt Register (PSL_ErrIVTE)

 Required

 PSL Key One Register (PSL_KEY1)

 Required

 PSL Key Two Register (PSL_KEY2)

 Required

 PSL Control Register (PSL_Control)

 Required

 AFU Download Control Register (AFU_DLCNTL)

 Optional

 AFU Download Address Register (AFU_DLADDR)

 Optional

 PSL Lookaside Buffer Invalidate Selection Register (PSL_LBISEL)

 Required

 PSL SLB Invalidate Entry Register (PSL_SLBIE)

 Required

 PSL SLB Invalidate All Register (PSL_SLBIA)

 Required

 PSL TLB Invalidate Entry (PSL_TLBIE)

 Required

 PSL TLB Invalidate All (PSL_TLBIA)

 Required

 PSL AFU Selection Register (PSL_AFUSEL)

 Required

 Privilege 2

 PSL Process and Thread Identification Register(PSL_PID_TID_An)

 Required

 Context Save/Restore Pointer Register(CSRP_An)

 Optional

 Accelerator Utilization Record Pointer Zero Register (AURP0_An)

 Optional (deprecated)

 Accelerator Utilization Record Pointer One Register (AURP1_An)

 Optional (deprecated)

 Storage Segment Table Pointer Zero Register (SSTP0_An)

 Required

 Storage Segment Table Pointer One Register (SSTP1_An)

 Required

 PSL Authority Mask Register(PSL_AMR_An)

 Required

 SLB Invalidate Entry Register (SLBIE_An)

 Required

 SLB Invalidate All Register (SLBIA_An)

 Required

 SLB Invalidate Selection Register (SLBI_Select_An)

 Required

 PSL Data Storage Interrupt Status Register(PSL_DSISR_An)

 Required

 PSL Data Address Register (PSL_DAR_An)

 Required

 PSL Data Segment Register (PSL_DSR_An)

 Required

 PSL Translation Fault Control Register (PSL_TFC_An)

 Required

 PSL Process Element Handle Register (PSL_PEHandle_An)

 Optional

 PSL Error Status Register (PSL_ErrStat_An)

 Required

 AFU Control Register (AFU_Cntl_An)

 Required

 AFU Error Register (AFU_ERR_An)

 Required

 PSL WED Register(PSL_WED_An)

 Required

 PCIe Configuration Space

 PCIe® Type 0 Configuration Space

 Required

 CAIA Vendor-Specific Extended Capability Structure

 Required

 AFU Descriptor for compliant AFUs

 Required



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