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 3.1. Organization of a CAIA-Compliant Accelerator

 Logically, the CAIA defines two functional components: the PSL and the AFU. The PSL in a CAIA-compliant accelerator provides the interface to the host processor. Effective addresses from an AFU are translated to physical addresses in system memory by the PSL. The PSL also provides miscellaneous management for the AFUs. Although the CAIA architecture defines interfaces for up to four AFUs per PSL, early implementations support only a single AFU. The AFU can be dedicated to a single application or shared between multiple applications. However, only the dedicated programming model is currently supported.

 Physically, a CAIA-compliant accelerator can consist of a single chip, a multi-chip module (or modules), or multiple single-chip modules on a system board or other second-level package. The design depends on the technology used, and on the cost and performance characteristics of the intended design point.

 Figure 3.1, “CAIA-Compliant Processor System” illustrates a  CAIA-compliant accelerator with several (n) AFUs connected to the PSL. All the AFUs share a single cache.


Figure 3.1. CAIA-Compliant Processor System

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