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 12.2. PCIe® MSI-X Capability

 The MSI-X capability mechanism is used to identify and configure the interrupt structure for a CAIA-compliant accelerator. The CAIA supports two MSI-X modes: single MSI-X table entry and full MSI-X table.

 When operating with a single MSI-X table entry, interrupts are not fully compliant with the PCIe architecture. The PCIe architecture requires a MSI-X table and a pending-bit array (PBA) in MMIO space. A CAIA-compliant accelerator does not use the MSI-X table or the PBA. In place of the table, the interrupt message address and data are constructed from the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers. See Chapter 8, Interrupts and Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)” for more information.

 When operating with a full MSI-X table, interrupts are compliant with the PCIe architecture. The MSI-X table and a pending bit array in MMIO space are used. The index into the MSI-X table is constructed from the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An Registers. See Chapter 8, Interrupts and Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)” for more information. The address and data presented for the interrupt is provided by the MSI-X table entry selected.


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