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 Chapter 12. PCIe® Configuration Overview

 The PCIe configuration space for a CAIA-compliant device follows the PCIe standard. The configuration registers in this section should only be accessed by system software using the PCIe Configuration Mechanism. See the I/O Design Architecture v2 (IODA2) (Version 2.4+) for more information about how to access these registers in a POWER system. The PCIe configuration facilities include the following sections:

 The PCE section of the CAIA is not intended to reproduce the PCIe standard for the configuration space but rather to define how the various configuration fields are used by a CAIA-compliant device. See the PCIe standard for more complete information on the PCIe configuration space.

 Note: The bit and byte numbering for the registers in the PCIe Configuration Environment is little endian. This is different than all other registers in the CAIA. Little-endian numbering refers to the following:

  • The least significant byte is at offset x'3' in a 32-bit word.

  • The least significant bit is number 0.

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