Revision history   OpenPOWER Library

 12.3. CAIA Vendor-Specific Extended Capability Structure

 The Vendor-Specific Extended Capability (VSEC) structure defines the unique capabilities of the CAIA-compliant device. The CAIA uses the PCIe capability list architecture to link a VSEC structure within the device's configuration space. The capability list anchor is at offset x'100' in the configuration space defined in Section 12.1, “PCIe® Type 0 Configuration Space”.

 Table 12.3, “VSEC Format” defines the format of the VSEC structure for CAIA-compliant devices.

 

Table 12.3. VSEC Format

Addr

VSEC Data

Byte 3 / Address 3

Byte 2 / Address 2

Byte 1 / Address 1

Byte 0 / Address 0

31 

30 

29 

28 

27 

26 

25 

24 

23 

22 

21 

20 

19 

18 

17 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

 0x0

 Next Capability Pointer

 Cap_Ver (0x1)

 Capability ID (0x000B)

 0x4

 VSEC Length (0x080)

 VSEC_Rev

 (0x0)

 VSEC ID (0x1280)

 0x8

 Reserved

 Mode Control

 Status

 Number of AFUs

 0xC

 CAIA Version

 PSL Revision Level

 0x10

 IL

 R

 IC

 Reserved

 Base Image Revision Level

0x14:
0x1C

 Reserved

 0x20

 AFU Descriptor Offset

 0x24

 AFU Descriptor Size

 0x28

 Problem State Offset

 0x2C

 Problem State Size

0x30:
0x3C

 Reserved

 0x40

 PSL Programming Port (optional)

 0x44

 PSL Programming Control (optional)

0x48:
0x4C

 Reserved

 0x50

 Flash Address Register (optional)

 0x54

 Flash Size Register (optional)

 0x58

 Flash Status / Control Register (optional)

 0x5C

 Flash Data Port (optional)

0x60:
0x7C

 Reserved


 

Table 12.4. VSEC Description

Field Name

VSEC Offset

Bits

Description

 Capability ID

 x'0'

 15:0

 This field identifies the type of capability structure. This field is set to x'000B' for a VSEC structure.

 Capability Version

 x'0'

 19:16

 The Capability Version field is defined by the PCI Special Interest Group (PCI-SIG). The value for this field should be x'1'.

 Next Capability Pointer

 x'0'

 31:20

 Pointer to the next capability structure in the list.

 A value of x'000' indicates that this VSEC is the last capability structure in the list. A nonzero value is a pointer to the next capability structure in the list.

 VSEC ID

 x'4'

 15:0

 This field identifies the type of VSEC structure. This field is set to x'1280' for CAIA-compliant devices.

 VSEC Revision

 x'4'

 19:16

 The revision level of the VSEC structure.

 For this level of the CAIA, the VSEC revision is x'0'.

 VSEC Length

 x'4'

 31:20

 The length, in bytes, of the VSEC structure included the header at offset x'0'. For this level of the CAIA, the VSEC length is x'080'.

 Number of AFUs

 x'8'

 7:0

 The number of AFUs is a read/write field that defines the number of AFUs supported by the device. System software can write this field to a value less than the power-on value to reduce the number of supported AFUs. After reducing the number of supported AFUs, system software must read back this field to determine if the device supports reducing the number of supported AFUs.

 For devices with a fixed PSL, this field will power-on to the number of supported AFUs.

 For devices that support a loadable PSL, this field will power-on with a value of x'0', if a PSL is not present at power on; or with the number of supported AFUs if a PSL is present at power on. This field can change, after a PSL is downloaded, to the number of supported AFUs by the downloaded PSL.

 Status

 x'8'

 15:8

 Status.

Bits

Description

15

Secondary PCIe Links for CAPI (read-only). This bit is used to indicate whether the corresponding PCIe link is an extension port used for more bandwidth.

0

Corresponding PCIe link is a primary PCIe port.

1

Corresponding PCIe link is a secondary PICe port for CAPI bandwidth enhancement.

14:13

MSI-X Address Selection (read-only).

This bit is used to indicate the type of MSI-X address supported by the device.

00

Fixed MSI-X address.

The ISN calculated by the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An values concatenated with 4 bits of zero (IVTE || 0x0) is ORed with a platform-specific constant (x'1000000000000000').

01

Single MSI-X table entry.

The ISN calculated by the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An values concatenated with 4 bits of zero (IVTE || 0x0) is ORed with the address provided in the entry of the MSI-X table pointed to by the MSI-X capability structure.

10

Full MSI-X table.

The ISN calculated by the PSL_IVTE_Offset_An and PSL_IVTE_Limit_An values is an index into the MSI-X table pointed to by the MSI-X capability structure.

12

Reserved.

11:10

Flash status (read-only).

00

Flash is not present.

01

Flash is present but can only be read.

10

Flash is present and can be programmed.

11

Reserved.

9

Loadable AFUs (read-only). This bit applies to all AFUs.

0

AFUs are not loadable unless the AFU is imbedded in the PSL image. AFU designs are fixed in hardware or part of the PSL image or hardware design.

1

AFUs are loadable. AFU designs can be downloaded by system software.

8

Loadable PSL (read-only)

0

PSL is not loadable. The PSL design is fixed in hardware.

1

PSL is loadable. The PSL design can be downloaded during initialization time.

 Mode Control

 x'8'

 23:16

 Mode Control Register.

Bits

Description

23:21

CAPI protocol area size.

At power-on or following a PCIe reset, this field indicates the sizes of the CAPI protocol area (BAR 4/5) supported by the CAIA-compliant device. Before enabling the device, system software must set this field to the size of the CAPI protocol area compatible with the host system. System software must set only one of these bits to '1'. The other bits must be set to '0'.

16

CAPI Protocol Enable.

This bit is used to enable the use of the CAPI protocol for the device. Devices that are only capable of CAPI mode initialize this bit to '1' and treat the bit as read-only.

100

1024 TB CAPI protocol area.

010

512 TB CAPI protocol area.

001

256 TB CAPI protocol area.

All other values are reserved.

Implementation Note:

System software must set the protocol area size to 256 TB for POWER8 systems.

20:17

Reserved.

16

CAPI Protocol Enable.

This bit is used to enable the use of the CAPI protocol for the device. Devices that are only capable of CAPI mode initialize this bit to '1' and treat the bit as read-only.

0

Operate as a PCIe device (PCIe mode).

1

Operate as a CAIA-compliant device (CAPI mode).

 Reserved

 x'8'

 31:24

 Reserved. Set to x'00000000'.

PSL Revision Level

x'C'

15:0

This field identifies the revision level of the PSL design. This field might not be valid until after the PSL is downloaded for devices that support loadable PSLs.

 CAIA Version

 x'C'

 31:16

 This field identifies the CAIA version that the device implements. This field might not be valid until after the PSL is downloaded for devices that support loadable PSLs. This field is divided into a major and minor number (X.y; where X is the major version number and 'y' is the minor version number).

Bits

Description

31:24

Major version number ('X').

23:16

Minor version number ('y').

 Base Image Revision Level

 x'10'

 15:0

 This field identifies the revision level of the base image for devices that support loadable PSLs. For programmable devices such as FPGAs, this field identifies the image contained in the on-adapter flash that is loaded during the initial program load (that is reset or power-on).

 Reserved

 x'10'

 27:16

 Reserved. Set to '0'.

Image Control

x'10'

29:28

Bits

Description

29

Request image reload on the next PERST.

This bit is used to cause a flash image load for programmable CAIA-compliant implementation. If this bit is set to '0', a power cycle of the adapter is required to load a programmable CAIA-compliant implementation from flash.

0

Assertion of PERST does not cause a flash image load.

1

Assertion of PERST causes a flash image load.

28

Image selection.

This bit is used to select which image is loaded when requesting an image reload on the next PERST. This bit has no effect on the power cycle of the adapter.

0

Factory flash image.

1

User flash image.

Reserved

x'10'

30

Reserved. Set to '0'.

Image Loaded

x'10'

31

Bits

Description

31

Image loaded (read-only).

This bit is the status of the image loaded into a programmable CAIA-compliant implementation. When this bit is set to '1' indicating that the factory image was loaded, it typically indicates that the user's image was corrupted.

0

Factory image.

1

User's image.

 Reserved

 x'14' - x'1C'

 31:0

 Reserved. Set to x'00000000'.

 AFU Descriptor Offset

 x'20'

 31:0

 This field specifies the offset of the AFU descriptor from the start of the privileged 2 BAR. The field contains bits 0:31 of a 48-bit offset. The lower 16-bits of the offset are always '0'. This is a read-only field.

 For CAIA-compliant devices with multiple AFUs, this field points to the AFU descriptor for AFU(0). The AFU descriptor offset for AFU(n) is located at:

AFU(n) descriptor =

(AFU Descriptor Offset * 64K) +

(AFU Descriptor Size * 64K * n)

 AFU Descriptor Size

 x'24'

 31:0

 This field specifies the maximum length of each AFU descriptor. The field is the maximum number of 64 KB blocks reserved for each AFU descriptor. This is a read-only field.

 Problem State Offset

 x'28'

 31:0

 This field specifies the offset of the AFU problem state area from the start of the privileged 2 BAR. The field contains bits 0:31 of a 48-bit offset. The lower 16-bits of the offset are always '0'. This is a read-only field.

 For CAIA-compliant devices with multiple AFUs, this field points to the problem state area for AFU(0). The problem state area offset for AFU(n) is located at:

AFU(n) problem state =

(Problem State Offset * 64K) +

(Problem State Size * 64K * n)

 Problem State Size

 x'2C'

 31:0

 This field specifies the maximum length of each AFU's problem state area. The field is the maximum number of 64 KB blocks of problem state area reserved by the PSL for each AFU. This is a read-only field.

 Reserved

 x'30' - x'3C'

 31:0

 Reserved. Set to x'00000000'.

 PSL Programming Port

 x'40'

 31:0

 This configuration register is used to load a PSL for devices that support a downloadable PSL. This register can also be used to download AFUs. Writes to this configuration register provide the programming information.

 The architecture for the programming port is device specific.

 PSL Programming Control

 x'44'

 31:0

 This configuration register is used to load a PSL for devices that support a downloadable PSL. This register can also be used to download AFUs. Writes to this configuration register provide the programming information.

 The architecture for the programming port is device specific.

 The architecture for the first CAPI programmable device follows:

Bits

Description

15:0

Free space (read-only).

The number of words that can be written to the configuration port. Implementations can have a queue for the programming information. This field allows software to poll for the amount of room in the programming information queue.

16

PR ready (read-only).

0

Internal reconfiguration machine is not ready.

1

Internal reconfiguration machine is ready.

17

PR done (read-only).

0

Internal reconfiguration machine is not done.

1

Internal reconfiguration machine is done.

20:18

Programming status.

000

Reset.

001

Programming error.

010

CRC error.

011

Programmnig stream incompatible.

100

Programming in progress.

101

Programming successful.

110

Reserved.

111

Reserved.

30:21

Reserved. Set to '0'.

31

PR request (R/W).

This bit is written to a '1' to request the programming of the PSL. This bit is reset to a '0' at the completion of the programming sequence or if an error is detected.

0

No programming request.

1

Request to program the PSL.

Reserved

x'48'-x'4C'

31:0

Reserved Set to x'00000000'

 Flash Address Register

 x'50'

 31:0

 This configuration register contains the starting address within the configuration flash device for program and read operations. The value in this register is a word (that is, 4-byte) address.

 Support of a configuration flash is optional.

 Flash Size Register

 x'54'

 31:0

 This configuration register contains the size for flash program and read operations.

 For program operations, the size is the number of blocks minus 1 where the block size is 64K words (256 KB).

 For read operations, the size is the number of words (4 bytes) minus 1.

 Support of a configuration flash is optional.

 Flash Status / Control Register

 x'58'

 31:0

 This configuration register contains the status and control for flash program and read operations.

Bits

Description

31

Flash ready (read-only).

0

Flash interface is not ready.

1

Flash interface is ready. A program or read request can be performed.

30

Operation done (read-only).

0

Current flash program or read operation is not complete.

1

Current fash program or read operation is complete.

27

Read request (write to '1', hardware reset to '0').

0

No read of flash requested.

1

Flash read request.

26

Program request (write to '1', hardware reset to '0')

0

No program of flash requested.

1

Flash program request.

15

Erase status (read-only)

0

Erase of flash is complete. (Next step is programming.)

1

Erase of flash is in process.

14

Programming status (read-only).

This bit is not synchronized with the programming write operations. Software should only use this bit for diagnostics.

0

Programming of flash is complete.

1

Programming of flash is in process.

13

Read status (read-only).

Implementations can perform a prefetch of flash. Software must only use this bit for diagnostics and not for a status when all reads by software have been performed.

0

Read of flash is complete.

1

Read of flash is in process.

9:0

Remaining operations (read-only).

This field contains the number of block remaining to be erased or programmed for a program request. For a read request, this field reflects the number of outstanding reads of the flash that are remaining. Updates of this field are not synchronized with configuration reads or writes. Software should only use this field for diagnostics.

All other bits are reserved and set to '0'.

Support of a configuration flash is optional.

 Flash Data Port

 x'5C'

 31:0

 This configuration register is used for writing the programming data for a program request and for reading the flash data for a read request.

Reserved

x'60'-x'7C'

31:0

Reserved Set to x'00000000'



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