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 12.1. PCIe® Type 0 Configuration Space

The Coherent Accelerator Interface Architecture (CAIA) uses PCIe type 0 configuration space for coherent accelerators connected using a coherent protocol tunneled over a PCI Express bus.

Table 12.1, “PCIe® Type 0 Configuration Header defines the PCIe type 0 configuration header for a CAIA-compliant device.

 Note: The configuration space is defined in little-endian format to conform to the PCIe standard. This diverges from the other facilities in the CAIA, which are defined in a big-endian format.

 Note: All the base address registers (BARs) are 64-bit addresses. Each BAR requires two configuration words in the type 0 header to represent a single address space.

 

Table 12.1. PCIe® Type 0 Configuration Header

Field Name

Configuration Header Offset

Bits

Description

 Device ID

 x'0'

 31:16

 The Device ID is an implementation-specific field.

 The Device ID field is the Device_ID[31:24] (byte 3) concatenated with the Device_ID[23:16] (byte 2).

 Vendor ID

 x'0'

 15:0

 The IBM Vendor ID is an implementation-specific field.

 The Vendor ID field is the Vendor_ID[31:24] (byte 3) concatenated with the Vendor_ID[23:16] (byte 2).

 Status

 x'4'

 31:16

 See the PCIe 3.0 Specification.

 Command

 x'4'

 15:0

 See the PCIe 3.0 Specification.

 Class Code

 x'8'

 31:8

 The Class Code is an implementation-specific value for bi-modal devices set to operate in PCIe mode.

 The Class Code field value is x'120000' for all CAPI devices, including bi-modal devices set to CAPI mode.

 The Class Code is the Class_Code[31:24] (byte 3) concatenated with the SubClass_Code[23:16] (byte 2) concatenated with the Programming_Interface[15:8] (byte 1).

 Revision ID

 x'8'

 7:0

 The Revision ID is an implementation-specific field.

 BIST

 x'C'

 31:24

 The built-in self test (BIST) is an implementation-specific field.

 Header Type

 x'C'

 23:16

 Read-only field. Set to x''00'.

 Master latency Timer

 x'C'

 15:8

 Read-only field. Set to x'00'.

 Cache Line Size

 x'C'

 7:0

 Read-only field. Set to x'00'.

 Base Address Register 0 (P2_Base_low)

 x'10'

 31:0

 Base Address Register 0 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, Base Address Register 0 is defined below:

  • Least significant 32-bits of the 64-bit base address for the Privileged 2/problem state register space (P2_Base).

  • Bits n:0 are read-only and always returned as '0' for reads of the base register; where 2 n is the size of the CAIA register map.

  • BAR 0/1 must be greater than or equal to 4 GB.

  • Default value: x'00000004'.

Note: Some implementations require the address specified by this BAR to be greater than or equal to 4 GB, so that 64-bit addressing is used when addressing the MMIO region.

Note: This register is represented as little-endian where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a dual port PCIe CAIA-compliant device.

 Base Address Register 1 (P2_Base_high)

 x'14'

 31:0

 Base Address Register 1 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, Base Address Register 1 is defined below:

  • Most significant 32-bits of the 64-bit base address for the Privileged 2/problem state register space (P2_Base).

  • Bits n:0 are read-only and always returned as '0' for reads of the base register; where 2 n is the size of the CAIA problem state register map.

  • BAR 0/1 must be greater than or equal to 4 GB.

  • Default value: x'00000000'.

Note: Some implementations require the address specified by this BAR to be greater than or equal to 4 GB so that 64-bit addressing is used when addressing the MMIO region.

Note: This register is represented as little-endian, where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a dual port PCIe CAIA-compliant device.

 Base Address Register 2 (P1_Base_low)

 x'18'

 31:0

 Base Address Register 2 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, Base Address Register 2 is defined below:

  • Least significant 32-bits of the 64-bit base address for the Privileged 1 register space (P1_Base).

  • Bits n:0 are read-only and always returned as '0' for reads of the base register; where 2 n is the size of the CAIA register map.

  • Default value: x'00000004'.

Note: Some implementations require the address specified by this BAR to be greater than or equal to 4 GB so that 64-bit addressing is used when addressing the MMIO region.

Note: This register is represented as little endian where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a dual port PCIe CAIA-compliant device.

 Base Address Register 3 (P1_Base_high)

 x'1C'

 31:0

 Base Address Register 3 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, the Base Address Register 3 is defined below:

  • Most significant 32-bits of the 64-bit base address for the Privileged 1 register space (P1_Base).

  • Bits n:0 are read-only and always returned as '0' for reads of the base register; where 2 n is the size of the CAIA problem state register map.

  • Default value: x'00000000'.

Note: Some implementations require the address specified by this BAR to be greater than or equal to 4 GB, so that 64-bit addressing is used when addressing the MMIO region.

Note: This register is represented as little endian where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a dual port PCIe CAIA-compliant device.

 Base Address Register 4

 (CAPI_Base_low)

 x'20'

 31:0

 Base Address Register 4 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, the Base Address Register 4 is defined below:

  • Least significant 32-bits of the 64-bit base address for the CAPI protocol area.

  • Bits 47:0 are read-only and always returned as '0' for reads of the base register.

  • System software must set BAR 4/5 to the CAPI Protocol address range compatible with the processor implementation.

  • Default Value: x'00000004'.

 This register is represented as little endian where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a dual port PCIe CAIA-compliant device.

 Base Address Register 5

 (CAPI_Base_high)

 x'24'

 31:0

 Base Address Register 5 is an implementation-specific field for bi-modal devices set to operate in PCIe mode.

 For all CAPI devices, including bi-modal devices set to CAPI mode, the Base Address Register 5 is defined below:

  • Most significant 32-bits of the 64-bit base address for the CAPI protocol area.

  • System software must set BAR 4/5 to the CAPI protocol address range compatible with the processor implementation.

  • Default Value: x'00000000'.

 This register is represented as little endian where the most significant bit is bit 63 and the least significant bit is bit 0. This register is not used for the secondary port of a a dual port PCIe CAIA-compliant device.

 Cardbus CIS Pointer

 x'28'

 31:0

 Read-only field.

 Set to x'00'.

 Subsystem ID

 x'2C'

 31:16

 The Subsystem ID is an implementation-specific field.

 The Subsystem ID field is the Subsystem_ID[31:24] (byte 3) concatenated with the Subsystem_ID[23:16] (byte 2).

 Subsystem Vendor ID

 x'2C'

 15:0

 The IBM Subsystem Vendor ID is an implementation-specific field.

 The Subsystem Vendor ID field is the Subsystem_Vendor_ID[31:24] (byte 3) concatenated with the Subsystem_Vendor_ID[23:16] (byte 2).

 Expansion ROM Base Address

 x'30'

 31:0

 See the PCIe 3.0 Specification.

 This configuration register is optional for a CAIA-compliant device.

 The contents of the ROM is implementation specific.

 Reserved

 x'34'

 31:8

 Read-only field. Set to x'00'.

 Capabilities Pointer

 x'34'

 7:0

 The Capabilities Pointer is an implementation-specific field.

 CAIA-compliant devices should include the vital product data (VPD) capability structure defined by the PCI Local Bus Specification (ID = x'03'). At a minimum, the VPD information should contain the part number (PN), engineering change level (EC), and serial number (SN) fields.

 Reserved

 x'38'

 31:0

 Read-only field. Set to x'00'.

 Max_Lat

 x'3C'

 31:24

 Read-only field. Set to x'00'.

 Min_Gnt

 x'3C'

 23:16

 Read-only field.

 Set to x'00'.

 Interrupt Pin

 x'3C'

 15:8

 Implementation-specific field.

 This value of this field has no effect when operating in CAPI mode.

 Interrupt Line

 x'3C'

 7:0

 Implementation-specific field.

 This value of this field has no effect when operating in CAPI mode.



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