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 10.1.17. PSL Error Interrupt Register (PSL_ErrIVTE)

 The PSL Error Interrupt Register (PSL_ErrIVTE) defines the interrupt level, which is generated when the PSL detects an error condition requiring attention from system software, typically the hypervisor. The PSL errors, that are reported using this interrupt level are errors that are not associated with any particular process or AFU slice.

 Note: The PSL_IVTE_Limit_An Register is not applied to the ErrIVTE.

 The PSL error conditions and status are implementation specific. For more information, see the implementation-specific documentation.

 System software should record the errors reported with this interrupt in the system error log.

 There is only one register for the PSL. Access to this register should be privileged. This register must be accessed using a single 64-bit store operation.

 Note: When resetting the interrupt status bit, system software should make sure the ErrIVTE field is also written to the current interrupt vector for errors reported to the hypervisor.

Access Type

Read/Write

 Base Address Offset

 P1_Base + x'0008'

Implementation Dependent

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Implementation Mask

ErrIVTE

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:30

 Implementation

Dependent

 Reserved for implementation-dependent PSL errors.

 Bits in this field are set to '1' if the PSL has detected the corresponding error condition. Additional status information about the error might be available in an implementation-specific register. Bits in this field are reset to '0' when the register is written with the corresponding bit set to '1'.

 31

 TE

Time-base error.

This bit is set with the PSL receives an error response when updating the time-base value. This bit is reset to '0' when this register is written with the TE bit set to '1'. After an error, time-base synchronization is stopped. The following procedure must be initiated to restart time-base synchronization.

  1. Clear the time-base error by writing PSL_ErrIVTE[TE] to '1'

  2. Disable time-base synchronization by writing PSL_Control[TB] to '0'.

  3. Clear the error and restart time-base synchronization in the host. (See the appropriate system specifications for the procedure.)

  4. Enable time-base synchronization by writing PSL_Control[TB] to '1'.

 32:47

 Implementation Mask

 Reserved for an implementation-dependent PSL error that can be masked.

 Bits in the fields are set to '0' if system software wants to receive an interrupt with the associated error bits [0:15]. Setting a bit in this field to '1' masks the error and an interrupt is not presented by the PSL.

 48:63

 ErrIVTE

 Error interrupt level.

 The field contains the interrupt source number presented when the PSL detects an error condition requiring attention from system software.


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