Revision history   OpenPOWER Library

 10.1.6. PSL Slice Error Register (PSL_SERR_An)

 The PSL Slice Error Register (PSL_SERR_An) defines the interrupt level, which is generated when the PSL detects an error condition requiring attention from system software, typically the hypervisor. There are two errors that are reported using this interrupt level: the PSL error associated with a slice but not a particular process and the hypervisor context time warning.

 Note: The PSL_IVTE_Limit_An Register is not applied to the ErrIVTE_Slice.

 The PSL error conditions and status are implementation specific. For more information, see the implementation-specific documentation.

 The hypervisor context time warning is generated when the AFU has not responded to a context save request from the PSL and the PSL_CtxTime[Warn_Hypervisor] time has expired.

 System software should record the errors reported with this interrupt in the system error log.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

 This register is optional for CAIA-compliant devices that support only a single AFU. System software can detect if this feature is supported by writing x'000000000000FFFF' to this register and reading back the contents. If a value of zero is returned, this feature is not supported. Any nonzero value indicates that the feature is supported.

 Note: When resetting the interrupt status bit, system software should make sure the ErrIVTE_Slice field is also written to the current interrupt vector for errors reported to the hypervisor.

  

Access Type

Read/Write

 Base Address Offset

 P1_Base | P1(n)) + x'28'; where n is an AFU number.

Implementation Dependent

AE

HC

 0

 1

 2

 3

 4

 5

 6

 7

 8

 9

 10

 11

 12

 13

 14

 15

 16

 17

 18

 19

 20

 21

 22

 23

 24

 25

 26

 27

 28

 29

 30

 31

Implementation Dependent

ErrIVTE_Slice

 32

 33

 34

 35

 36

 37

 38

 39

 40

 41

 42

 43

 44

 45

 46

 47

 48

 49

 50

 51

 52

 53

 54

 55

 56

 57

 58

 59

 60

 61

 62

 63

Bits

Field Name

Description

 0:29

 Implementation

Dependent

 Reserved for implementation-dependent PSL errors.

 Bits in this field are set to '1' if the PSL has detected the corresponding error condition. Additional status information concerning the error might be available in an implementation-specific register. Bits in this field are reset to '0' when the this register is written with the corresponding bit set to '1'.

 30

 AE

 Set to '1' when the AFU asserts an error in AFU directed mode. There is additional status information provided in the corresponding AFU_ERR_An. This bit is reset to '0' when this register is written with the AE bit set to '1'.

 31

 HC

 Set to '1' if the PSL_CtxTime[Warn_Hypervisor] timer interval expires. There is no additional status information provided for this interrupt. This bit is reset to '0' when this register is written with the HC bit set to '1'.

 32:47

 Implementation

Dependent

 Reserved for implementation-dependent PSL errors.

 Bits in this field are set to '1' if the PSL has detected the corresponding error condition. Additional status information concerning the error might be available in an implementation-specific register. Bits in this field are reset to '0' when the this register is written with the corresponding bit set to '1'.

 48:63

 ErrIVTE_Slice

 Error interrupt level.

 The field contains the interrupt source number presented when the PSL detects an error condition requiring attention from system software.

  


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