Revision history   OpenPOWER Library

 10.1.20. PSL Control Register (PSL_Control)

 The PSL Control Register (PSL_Control) contains general control settings for the overall PSL.

 Setting the PSL cache flush request (Fr) bit causes the PSL to flush the data from the cache. For proper operation, the AFUs should be stopped before issuing this request to avoid new data from being read back into the cache. To continue normal operation from a suspended state, the PSL_Control[Fr] must be set to zero.

 There is only one register for the PSL. Access to this register should be privileged. This register must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 P1_Base + x'0020'

Reserved

Fs

Rsvd

Fr

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

TB

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:27

 Reserved

 Reserved

 28:29

 Fs

 PSL cache flush status. This is a read-only field. Data written to this field is ignored.

00

Normal PSL operation.

01

PSL cache operations in process (some implementations can choose not to implement this state).

11

PSL cache flush operation complete.

 30

 Reserved

 Reserved.

 31

 Fr

 PSL cache flush request.

0

Normal PSL operation.

1

PSL cache flush operation request.

Programming Note:

The PSL cache flush request (Fr) bit provides system software the ability to flush the PSL's cache in a single operation. For proper operation, all the AFUs should be stopped before issuing this request. Any pending transactions are allowed to complete.

 32:62

 Reserved

 Reserved.

63

TB

Time-base enable.

 Enable the synchronization of the PSL's time base with the host system.

0

Time-base synchronization disabled.

1

Time-base synchronization enabled.

Programming Note:

he PSL cache flush request (Fr) bit provides system software the ability to flush the PSL's cache in a single operation. For proper operation, all the AFUs should be stopped before issuing this request. Any pending transactions are allowed to complete.

 Changing the TB bit from '0' to '1' causes the PSL to start the synchronization of the PSL's local time base with the time base of the host system's time base. The time-base synchronization process continues to keep the PSL's local time base synchronized with the host system's time base as long as the TB bit is set to '1'. Changing the TB bit from '1' to '0' causes the PSL to stop the synchronization process.

 The host system must be enabled for the synchronization process before setting the TB bit.


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