Revision history   OpenPOWER Library

 10.1.3. PSL AFU Memory Base Address Register (PSL_AMBAR_An)

 The PSL AFU Memory Base Address Register (PSL_AMBAR_An) contains the starting address in main storage of the AFU's memory that is mapped into system memory. The storage area defined by the PSL_AMBAR_An can be marked as cacheable storage in the hardware page table. The contents of this register is typically a subset of a larger storage region defined by the host processor's External Memory Base Address Register. The storage regions defined for all AFUs must not overlap and must be fully contained in the larger storage region defined by the host processor's External Memory Base Address Register.

 This register is always initialized by the hypervisor when the AFU memory controller is enabled for the selected programming mode. The AFU memory controller model is never virtualized. This register is not valid when the AFU memory controller is not enabled for the programming model (that is, there is no AFU memory mapped into system memory).

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

 This facility is optional. Reads of this register must return zeros when the AFU memory controller is not supported or not enabled for the programming model. System software can detect if this feature is supported by writing x'0FFFFFFFFFFFF03F' to this register and reading back the contents. If a value of zero is returned, this feature is not supported. Any nonzero value indicates that the feature is supported.

  

Access Type

Read/Write

 Base Address Offset

 (P1_Base | P1(n)) + x'10'; where n is an AFU number.

E

Rsvd

AMBAR

 0

 1

 2

 3

 4

 5

 6

 7

 8

 9

 10

 11

 12

 13

 14

 15

 16

 17

 18

 19

 20

 21

 22

 23

 24

 25

 26

 27

 28

 29

 30

 31

AMBAR

Reserved

AMSIZE

 32

 33

 34

 35

 36

 37

 38

 39

 40

 41

 42

 43

 44

 45

 46

 47

 48

 49

 50

 51

 52

 53

 54

 55

 56

 57

 58

 59

 60

 61

 62

 63

  

Bits

Field Name

Description

 0

 E

 Enable

 When this bit is set to '1', the AFU's memory is mapped into the system's address space.

0

AMBAR disabled.

1

AMBAR enabled.

Implementation Note:

 If the PSL implementation does not support mapping AFU memory into the system memory address space (LPC operation), this field must be read-only and returned as a '0'. System software can read the initial value or write a '1' to this field to determine the PSL's capability to support LPC operation.

 1:3

 Reserved

 Reserved.

 4:51

 AMBAR

 AFU's memory origin (real address of AFU's memory that is mapped into system memory).

 The AMBAR field in PSL_AMBAR_An contains the high-order 48 bits of the 60-bit real address of the AFU's memory. The AFU's memory is thus constrained to lie on a 2 12 byte (4 KB) boundary at a minimum. The number of low-order zero bits in AMBAR must be greater than or equal to the value in AMSIZE.

 For implementations that support a real address size of only m bits, where m is less than 62, the upper bits of the AFU's memory origin are treated as reserved bits. Software must set them to zeros.

 52:57

 Reserved

 Reserved.

58:63

AMSIZE

Encoded size of AFU's memory.

The AMSIZE field in PSL_AMBAR_An contains an integer giving the number of bits (in addition to the minimum of 12 bits) that are used to address the AFUs memory. This number must not exceed 28.


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