Revision history   OpenPOWER Library

 10.1.26. PSL TLB Invalidate Entry (PSL_TLBIE)

A write to the PSL TLB Invalidate Entry (PSL_TLBIE) causes the Valid (V) bit in the matching entries of the TLB to be set to '0', making the entries invalid. The remaining fields of each entry are undefined. For any value other than '00' in the Invalidation Qualifier (IQ) field, the PSL_LBISEL Register must be written before writing the PSL_TLBIE Register.

 This register is typically used by the hypervisor when TLB Invalidate instructions are not broadcast to all processing elements in the system. This register is similar to the TLB Invalidate Entry Local (POWER processor instruction).

 There is only one register for the PSL. Access to this register should be privileged. This register must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 P1_Base + x'00A0'

 Register Write Field Description:

AVA

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

AVA

AVA/LP

IQ

B

AP/AVAL

L

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:43

 AVA

 Abbreviated virtual address.

 This field contains bits 14:57 of the virtual address translated by the TLB to be invalidated.

 For more information on the details of this field, see the Power Architecture Book III.

 44:51

 AVA/LP

 Abbreviated virtual address (AVA) when PSL_TLBIE[L] = '0'.

 When the L bit is set to zero, this field contains bits 58:65 of the virtual address translated by the TLB to be invalidated.

 Large Page Size Selector (LP) when PSL_TLBIE[L] = '1'.

 When the L bit is set to one, this field contains the Large Page size selector.The size of the base page and actual page size selected by the LP field is implementation dependent. The number of concurrent page sizes supported is also implementation dependent. The bits represented by "z" in this field specify the base page size and actual page size. The bits represented by "r" are the lower bits of the virtual address. Depending on the page size selected, the bits in this field represented by "r" might be concatenated with the VPN field to determine which entries are invalidated.

rrrrrrrr

TLB_Invalidate_Entry[L] = '0'.

rrrrrrrz

If TLB_Invalidate_Entry[L] = '1', actual page size ≥ 8 KB.

rrrrrrzz

If TLB_Invalidate_Entry[L] = '1', actual page size ≥ 16 KB.

...

zzzzzzzz

If TLB_Invalidate_Entry[L] = '1', actual page size ≥ 1 MB.

 Software should set the least-significant bit of the LP field to the same value as the LS bit for compatibility with implementations that only support two large page sizes.

 For more information on the details of this field, see the Power Architecture Book III.

 52:53

 IQ

 TLB invalidation qualifier (IQ).

 The IQ field is used to selectively invalidate only the TLB entries based on the "LPID" or "PID and LPID" combination. The value for the PID and LPID is defined by the PSL_LBISEL Registers.

00

Invalidate all TLBs.

01

Invalidate the TLBs matching the LPID.

11

Invalidate the TLBs matching the LPID and PID.

Note: This field replaces the IQ field in the Power Architecture for a tlbiel instruction. For CAIA-compliant implementations, the IQ field is assumed to always be '00'.

 54:55

 B

 Segment size selector.

 The segment size selector defines the size of the segment used for the TLB. The segment size selector field must match the TLB entry being invalidated.

 56:62

 AP/AVAL

 Actual page size (AP) when PSL_TLBIE[L] = '0'.

 When the L bit is set to zero, the base page size is 4 KB and bits 56:58 specify the actual page size of the TLB entry to be invalidated. System software must set bits 56:58 to the encoding (SLBEL||LP) for the actual page size specified by the PTE.

 Abbreviated virtual address, lower (AVAL) when PSL_TLBIE[L] = '1'.

 When the L bit is set to one, this field must contain the lower bits (starting with bit 58) of the virtual address translated by the TLB to be invalidated. The number of bits used by the hardware in this field is determined by the base page size.

 For more information on the details of this field, see the Power Architecture Book III.

 63

 L

 Large page indicator

0

Page is small (4 KB).

1

Page is large. See LP field.

 Register Read Field Description:

Reserved

Max_TLBIEs

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

TLBIEs_Pending

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:23

 Reserved

 Set to zeros.

 24:31

 Max_TLBIEs

 Maximum number of TLBIE commands supported.

 This field indicates the maximum number of outstanding TLB invalidate entry commands supported. This value of this field is implementation-dependent.

 32:55

 Reserved

 Set to zeros.

 56:63

 TLBIEs_Pending

 Number of TLBIE commands pending.

 The TLBIEs_Pending field indicates the number of TLBIE commands currently outstanding. This field is used to determine when the previously issued TLB invalidations are complete. Issuing any additional TLB invalidates (that is, writing this register) when the number of invalidation pending is at the maximum can result in a TLB invalidate being lost or discarded.

x'00'

No TLB invalidate entry commands are pending.

x'01'

One TLB invalidate entry command is pending.

...

x'FF'

255 TLB invalidate entry commands still pending.


loading table of contents...