Revision history   OpenPOWER Library

 10.1.12. PSL Slice Control Register (PSL_SCNTL_An)

 The PSL Slice Control Register (PSL_SCNTL_An) allows system software to govern the operation of a single slice of the PSL.

 The Programming Model (PM) field sets the programming model for the corresponding AFU slice.

 Setting the Suspend Control (Sc) bit causes the corresponding PSL slice to stop executing transactions for the corresponding AFU. Requests from the AFU might still be accepted while the PSL is suspended. To continue normal operation from a suspended state, the PSL_SCNTL_An[Sc] must be set to zero.

 Setting the Purge (Pc) bit in this register causes the PSL to terminate all requests queued for the corresponding AFU. AFU requests are not accepted while the PSL is in the purge state. To continue normal operation after the purge operation, the PSL_SCNTL_An[Pc] must be set to zero.

 To resume normal PSL operation:

  • After a PSL hardware error, the Purge Sequence (Pc and Ps) must be issued before setting normal PSL transaction processing.

  • After a PSL suspend, the Suspend Command bit (Sc) must be set to normal PSL transaction processing.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P1_Base | P1(n)) + x'A0'; where n is an AFU number.

Reserved

CR

PM

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

Ps

Reserved

Pc

Reserved

Ss

Reserved

Sc

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:14

 Reserved

 Reserved.

 15

 CR

 Configuration required.

 When the CR bit is set, a configuration download of the AFU is required. This bit is set by system software at initialization or when an AFU is deallocated. This bit prevents an AFU from being enabled until an image is downloaded.

0

A download of an AFU is not required.

1

A download of an AFU is required. (Prevents the AFU from being enabled.)

Note: This field replaces the Machine Check Interrupt Enable (ME) field in the Power Architecture Machine State Register (MSR) definition. For CAIA-compliant implementations, machine check interrupts are not sourced.

 16:31

 PM

 Programming model type.

x'0000'

Shared: PSL-controlled time-sliced virtualization of the AFU.

x'0001'

Dedicated operating system: PSL-controlled time-sliced virtualization of the AFU.

x'0002'

Dedicated process: No AFU virtualization.

x'0004'

AFU directed-shared: AFU-controlled process element selection virtualization.

 32:37

 Reserved

 Reserved.

 38:39

 Ps

PSL transaction purge status. This is a read-only field. Data written to this field is ignored.

00

Purge request not outstanding.

01

Purge of PSL transactions in process (some implementations can choose not to implement this state).

11

Purge of PSL transactions is complete.

 40:47

 Reserved

 Reserved.

 48

 Pc

 Purge all PSL transactions from the associated AFU.

0

No purge of PSL transactions requested.

1

Purge PSL transactions request.

 49:53

 Reserved

 Reserved.

 54:55

 Ss

 PSL transaction queue suspend status. This is a read-only field. Data written to this field is ignored.

00

Normal PSL transaction operation.

01

Suspend of PSL operation in process (some implementations can choose not to implement this state).

 56:62

 Reserved

 Reserved.

 63

 Sc

 Suspend control. Suspend PSL operation.

0

Normal PSL operation.

1

Suspend PSL operation request.

Programming Note:

 The PSL Suspend control (Sc) bit allows system software to stop the PSL from processing a transfer request from the associated AFU. Pending transactions are allowed to complete. This bit is useful for handling page migration in the system.

[Note]Note

 The programming model type is broken down in several fields. The lower bits (bits 24:31) are an encode of the model type and the upper bits (bits 16:23) are enables for various features of the PSL. The model types are the various forms of virtualization: time sliced and AFU directed. Each model has two forms of virtualization: shared between partitions and dedicated to a partition. The functions enables are in the following order.

  • Check LPID of PBT command - bit 22

  • Check PID of PBT command - bit 21

  • Lowest Point of Coherency (LPC) enable - bit 20

 Mode 0x0004 is intended for XSL.

 This note is not intended to be an architectural statement of the bit locations. As new models and combinations are defined, the Programming Model field will be updated. Software cannot depend on the bit locations for the various features.


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