Revision history   OpenPOWER Library

 10.1.1. PSL State Register (PSL_SR_An)

 PSL State Register (PSL_SR_An) contains configuration information for the corresponding PSL slice.

 This register is initialized by the hypervisor or from the process element. The process element information is used when the PSL Scheduled Processes Area is enabled (PSL_SPAP_An[V] = '1').

 When the AFU is operating in a virtualized programming model, the data returned when reading this register is indeterminate. CAIA-compliant devices should return the corresponding process element data when an interrupt is pending for diagnostic purposes.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P1_Base | P1(n)) + x'00'; where n is an AFU number.

SF

Rsvd

HV

Reserved

 0

 1

 2

 3

 4

 5

 6

 7

 8

 9

 10

 11

 12

 13

 14

 15

 16

 17

 18

 19

 20

 21

 22

 23

 24

 25

 26

 27

 28

 29

 30

 31

Reserved

RU

PR

PTS

ISL

TC

PF

Rsvd

SC

R

Rsvd

MP

LE

 32

 33

 34

 35

 36

 37

 38

 39

 40

 41

 42

 43

 44

 45

 46

 47

 48

 49

 50

 51

 52

 53

 54

 55

 56

 57

 58

 59

 60

 61

 62

 63

Bits

Field Name

Description

 0

 SF

 Sixty-four bit mode.

0

AFU effective addresses are interpreted as 32-bit values.

1

AFU effective addresses are interpreted as 64-bit values.

 1:2

 Reserved

 Reserved.

 3

 HV

 Hypervisor state.

0

AFU is not operating in a hypervisor state.

1

AFU is operating in a hypervisor state if PSL_SR_An[PR] = '0'; otherwise,

AFU is not operating in hypervisor state.

Programming Note:

 The privilege state of an AFU is determined by PSL_SR_An[HV] || PSL_SR_An[PR].

00

AFU is operating in a privileged state..

01

AFU is operating in a problem state.

10

10 AFU is operating in a privileged and hypervisor state.

11

10 AFU is operating in a problem state.

 4:47

 Reserved

 Reserved.

 48

 RU

 Hot/cold reference array update control.

 When operating with the new PTE format enabled, a hot/cold reference array is also maintained in system memory. The PSL also sends special operations to the system to update this structure if this bit is set to '1'.

0

Updates of the HCA structure are not performed.

1

Updates of the HCA structure are performed.

 49

 PR

 Problem state.

0

The PSL has privileged-state access to pages.

1

The PSL has problem-state access to pages.

The PSL problem state (PR) bit is set by system software based on the use of the associated AFU. If the AFU is to be a system software resource (not under direct control of an application) and the function requires the AFU to issue memory requests with privileged-state access to pages, this bit must be cleared. If the AFU function is controlled by an application, its access must be restricted to problem state by the PR bit. The problem state control bit interacts with the Ks and Kp storage key bits in the SLB in combination with the Page Protection (PP) bits in the page table, as defined in Power ISA, Book III . The problem-state control is only effective in PSL translation on state (R = '1').

 50:52

 PTS

 PTE time base selection.

 The PTE time base selection field controls the granularity for updating the PTE time base field in the new PTE format. These bits also select which bits of the time base are used for updates of the hot/cold reference array (HCA structure in system memory). This field is only used when the new format is selected.

000

Reserved

001

0.5 s

010

1 s

011

2 s

100

4 s

101

8 s

110

16 s

111

32 s

 53

 ISL

 Ignore segment large-page specification.

 When ISL mode is enabled, and address translation is enabled, and the PSL is not in hypervisor state; address translation is performed as if the contents of SLB L||LPbits are '000'. This also applies for virtual addresses provided in the process element. When address translation is disabled, the setting of the ISL bit has no effect. The setting of the ISL bit has no effect on translation invalidations. Hypervisor state and operating with translation disabled is not supported by the CAIA so this bit always has an effect on the address translation mechanism.

0

ISL disabled

1

ISL enabled

Note: This field replaces the single-step trace enable (SE) field in the Power Architecture Machine State Register (MSR) definition. For CAIA-compliant implementations, the trace facilities are controlled by a different means.

 54

 TC

 Translation control.

0

Secondary hash of the page table search is enabled.

1

Secondary hash of the page table search is disabled.

Note: This field replaces the branch trace enable (BE) field in the Power Architecture Machine State Register (MSR) definition. For CAIA-compliant implementations, the trace facilities are controlled by a different means.

 55

 PF

 PTE format.

 This field controls the format of the page table entry (PTE). When this bit is set to '0', the format is defined by the Power Architecture. When this bit is set to '1', the format is implementation specific. Bits 48 and 50:52 are used as control bits for the new PTE format.

0

PTE format specified by the Power Architecture.

1

New implementation-specific PTE format.

 56:57

 Reserved

 Reserved.

 58

 SC

 Segment translation control.

0

Secondary hash of the segment table search is enabled.

1

Secondary hash of the segment table search is disabled.

Note: This field replaces the Instruction Relocate (IR) field in the Power Architecture Machine State Register (MSR) definition. The CAIA does not treat instruction and data fetches from an AFU differently.

 59

 R

 Relocate.

0

PSL translation is off.

1

PSL translation is on.

Programming Note:

The PSL Relocate (R) bit controls how effective addresses are translated into  real addresses. If the relocate control specifies translation off (R = '0'), the effective addresses are treated as real addresses. If the relocate control is enabled (R = '1'), the effective addresses are translated. The SLB, TLB, and page table facilities are used to translate the effective address to a virtual address, and then to a real address.

 60:61

 Reserved

 Reserved.

 62

 MP

 Master process.

 The Master Process bit identifies the process as having authority to control and manage the resource of the AFU. This bit is provided to the AFU by the PSL.

0

The corresponding process is a user process.

1

The corresponding process is a master process and enabled to control and manage the resources of the AFU.

 63

 LE

 Little endian.

 The data being accessed by the AFU is stored in a little-endian format, meaning the least significant byte first. The bit does not change the operation of the PSL. The PSL only provides this bit to the AFU in the dedicated or time-sliced programming models. The method for an AFU to determine the setting of this bit for the AFU-directed programming models is implementation dependent.

0

Big-endian format.

1

Little-endian format.


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