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 10.2.5. PSL Authority Mask Register(PSL_AMR_An)   

 The Virtual Page Class Key Protection mechanism described in the Power ISA, Book III provides a means to assign pages of storage to one of 32 classes. The PSL Authority Mask Register (PSL_AMR_An) allows software to modify the access permissions for all accelerator function unit accesses. The PSL_AMR_An is similar to the AMR described the Power ISA, Book III .

 The access mask for each class defines the access permissions that apply to all read and write operations from the corresponding AFU. The key field value in the page table entry (PTE) corresponds to the class number for each translated virtual address. The key field value in the PTE is used to select the corresponding key in the AMR for the class of the page of storage. For more information about the LPAR, see Power ISA, Book III .

 Privilege software must initialize the contents of the PSL_AMR_An for the dedicated-process programming model. For the shared or AFU-directed programming model, the content of this register is automatically updated by the PSL using the information in the process element. The new value of the PSL_AMR_An is the process element authority mask (PEAM) value in the process element, masked with the value in the PSL Authority Mask Override Register (PSL_AMOR_An). The store data is masked with the PSL_AMOR_An. The following equations define the value loaded into the PSL_AMR_An Register:

Stores to the privileged 1 memory map address:

                              

PSL_AMOR_An = store_data;

where store_data is the data written using a processor store instruction.

                              

Stores to the privileged 2 memory map address:

                              

PSL_AMR_An = (PSL_AMR_An & ~PSL_AMOR_An) | (store_data & PSL_AMOR_An);

                              

where store_data is the data written using a processor store instruction.

                              

PSL update using the AMR value in the process element:

                              

PSL_AMR* = (PSL_AMR_An & ~PSL_AMOR_An) | (PEAM & PSL_AMOR_An);

                              

where PEAM is the data read from the process element by the PSL.

                              

* The PSL_AMR value is used for translation but is not placed into the PSL_AMR_An Register.

This register is initialized by the operating system or from the process element. The process element information is used when the PSL scheduled processes area is enabled (PSL_SPAP_An[V] = '1').

When the AFU is operating in a virtualized programming model, the data returned when reading this register is indeterminate. CAIA-compliant devices should return the corresponding process element data when an interrupt is pending for diagnostic purposes.

There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 P2_Base | P2(n)) + x'0030'; where n is an AFU number.

Key0

Key1

Key2

Key3

Key4

Key5

Key6

Key7

Key8

Key9

Key10

Key11

Key12

Key13

Key14

Key15

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Key16

Key17

Key18

Key19

Key20

Key21

Key22

Key23

Key24

Key25

Key26

Key27

Key28

Key29

Key30

Key31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

  

Bits

Field Name

Description

 2*x

 Keyx[0]

 Bit 0 of the access mask for class number x; where 0 x 31.

 Write permissions for AFU writes (afu_wr) to virtual pages that contain a key of class x.

0

Writes are permitted.

1

Writes are not permitted.

 (2*x) + 1

 Keyx[[1]

 Bit 1 of the access mask for class number x; where 0 x 31.

 Read permissions for AFU reads (afu_rd) from virtual pages that contain a key of class x.

0

Reads are permitted.

1

Reads are not permitted.

  


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