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 10.2.13. AFU Control Register (AFU_Cntl_An)

 The AFU Control Register (AFU_Cntl_An) allows system software to govern the operation of a single slice of the PSL.

 Setting the AFU Slice Enable (E) bit to a '1' causes a start command to be issued to the AFU slice. System software must wait for the status of the AFU to be set to running (AFU_Cntl_An[ES] = '100') before issuing any MMIO to the AFU in a dedicated-process programming model. Software should implement a timeout for enabling an AFU. If the timeout expires and the ES and RS fields are '000' and '00' respectively, then an error was detected by the PSL while enabling the AFU. An error can also be detected if the ES field transitions from a nonzero value to zero. The timeout value should be larger than the PSL implementation-dependent timeout.

 Note: The status fields can transition to other states. Software must wait for the AFU Slice Reset Status to be '10' before setting the AFU Slice Enable (E) to a '1'.

 Setting the AFU Slice Reset (RA) to a '1' causes a reset command to be issued to the AFU slice. System software must wait for the status of the reset to be complete (AFU_Cntl_An[RS] = '10') before enabling the AFU. The reset sequence also causes the AFU to be disabled. The final states of the AFU Slice Enable Status (ES) and the AFU Slice Reset Status (RS) fields are '000' and '10' respectively, after resetting the AFU. Software should implement a timeout for resetting an AFU. If the timeout expires and the ES and RS fields are '000' and '00' respectively, then an error was detected by the PSL while resetting the AFU. An error can also be detected if the RS field transitions from a nonzero value to zero.The timeout value should be larger than the PSL implementation-dependent timeout.

 If an error is detected while enabling or resetting an AFU, the AFU should be either downloaded again (for downloadable AFUs) or the CAIA-compliant adapter reset.

 The reset and enable status fields (ES, RS) can change when the slice is operating in a virtualized programming model. As part of a switching context, the PSL performs resets and enables of the AFU slice. See Chapter 7, Context Management for more information.

 Note: The AFU slice enable and reset bit are write only. The status fields for the corresponding request bits indicate when the operation requested has completed.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P2_Base | P2(n)) + x'0090'; where n is an AFU number.

ES

E

RS

Rsvd

RA

Reserved

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:2

 ES

 AFU slice enable status. Read only.

 The AFU slice enable status field contains the status of enabling or disabling the AFU.

000

AFU slice disabled. AFU does not respond to MMIO in the dedicated-process model.

010

AFU slice enabled/disable pending.

011

AFU slice enabled pending. Fetching process state for dedicated process.

100

AFU slice enabled. Reset and start commands are complete.

 3

 E

 AFU slice enable.

 The AFU slice enable bit controls the start and reset commands to the AFU slice.

0

AFU slice disabled.

1

AFU slice enabled.

 4:5

 RS

 AFU slice reset status. Read only.

 The AFU slice reset status field contains the status of the reset of the AFU.

01

AFU slice not reset.

01

AFU slice reset pending.

10

AFU slice reset sequence is complete.

 6

 Reserved

 Reserved.

 7

 RA

 AFU slice reset. Write only.

0

AFU slice reset not issued.

1

Issue a reset to the AFU slice.

 8:63

 Reserved

 Reserved.


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