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 10.2.7. PSL Data Storage Interrupt Status Register(PSL_DSISR_An) 

 The PSL Data Storage Interrupt Status Register (PSL_DSISR_An) contains the status that defines the cause of the PSL data storage interrupt. The function of this register is similar to the POWER Data Storage Interrupt Status Register (DSISR). For more information, see the Power ISA, Book III .

 The content of this register is set by the PSL when a data segment fault (segment table miss) occurs, data storage fault (page table miss) occurs, or a PSL error is detected. The register is reset to zero when the current outstanding fault is either restarted, continued, indicated as an address error, or acknowledged by a write to the PSL Translation Fault Control Register (PSL_TFC_An).

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read Only

 Base Address Offset

 (P2_Base | P2(n)) + x'0060'; where n is an AFU number.

DS

DM

ST

UR

PE

AE

OC

Reserved

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Rsvd

M

Rsvd

P

A

S

Reserved

K

Reserved

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0

 DS

 Set to '1' if the segment is not found. Bits 32:63 of this register are undefined if this bit is set. This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 1

 DM

 Set to '1' if the PTE is not found (same as the M bit) or for a protection fault. Bits 32:63 of this register are defined as shown below. This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 2

 ST

 Set to '1' if the PTE is not found for the segment table pointer (SSTP0_An || SSTP1_An). This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 3

 UR

 Set to '1' if the PTE is not found for the accelerator utilization record pointer (AURP0_An || AURP1_An). This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 4

 PE

 Set to '1' if the PSL has detected an error for the corresponding slice. The reason for the error is implementation specific. This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

Note: This is a nontranslation fault interrupt.

 5

 AE

 Set to '1' if the AFU has detected an error and is not able to post the error directly to the associated application. The reason for the error is indicated in the AFU Error Register (AFU_ERR_An). This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

Note: This is a nontranslation fault interrupt.

 6

 OC

 Set to '1' if the operating system context warning interval expires. This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

Note: This is a nontranslation fault interrupt.

 7:32

 Reserved

 Set to zeros.

 33

 M

 Set to '1' if the PTE is not found.

 This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 34:35

 Reserved

 Set to zeros.

 36

 P

 Set to '1' if the access is not permitted by the storage protection mechanism.

 This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 37

 A

 Set to '1' if an AFU lock type access is to page marked write through or caching inhibited.

 This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 38

 S

 Set to '1' if the access was an afu_wr or anafu_zero operation.

 This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 39:41

 Reserved

 Set to zeros.

 42

 K

 Set to '1' if the access is not permitted by the virtual-page class key protection.

 This bit is reset to '0' when the corresponding PSL_TFC_An Register is written.

 43:63

 Reserved

 Set to zeros.

  


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