Revision history   OpenPOWER Library

 10.2.6.2. SLB Invalidate All Register (SLBIA_An)

 A write to the SLB Invalidate All Register (SLBIA_An) causes the valid (V) bit in all entries of the SLB to be set to '0', making the entries invalid. The remaining fields of each entry are undefined.

 This facility is used by the system software to invalidate any noncoherent caches of the segment table or translations using the segment entries.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P2_Base | P2(n)) + x'0048'; where n is an AFU number.

 Register Write Field Description:

Reserved

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

IH

IQ

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:58

 Reserved

 Set to zeros.

 59:61

 IH

 SLB invalidation hint (IH).

 The IH field is provided by system software as a hint that can be used to selectively invalidate entries in the implementation-specific look aside information.

000

Invalidate all implementation-specific lookaside information. (This is not a hint.)

001

Preserve implementation-specific lookaside information having a class value of '0'.

010

Preserve implementation-specific lookaside information created when MSR[IR/DR] = '0'.

(This encoding is not valid for PSL implementations. Specific to the POWER architecture.)

110

Preserve implementation-specific lookaside information created when MSR[HV] = '1', MSR[PR] = '0', and MSR[IR/DR] = '0'.

(This encoding is not valid for PSL implementations. Specific to the POWER architecture.)

Other

All other IH values are reserved.

 62:63

 IQ

 SLB invalidation qualifier (IQ).

 The IQ field is used to selectively invalidate only the SLB entries based on the PID. The value for the PID is defined by the SLBI_Select_An Register.

00

Invalidate all SLBs.

01

Reserved.

11

Invalidate the SLBs matching the PID.

 Register Read Field Description:

Reserved

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

P

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

  

Bits

Field Name

Description

 0:30

 Reserved

 Set to zeros.

 31

 Reserved

 Set to one.

 This field indicates the maximum number of outstanding SLB Invalidate All commands supported. This field is set to one for TLB Invalidate All commands.

 32:62

 Reserved

 Set to zeros.

 63

 P

 SLB invalidations pending.

 The SLB invalidation pending (P) field is used to determine when the previously issued SLB invalidations are complete. Issuing any additional SLB invalidates (that is, writing this register) when the number of invalidation pendings is at the maximum, might result in an SLB invalidate being lost or discarded.

0

No SLB invalidate all commands are pending.

1

An SLB invalidate all command is pending.

[Note]Note

 The SLB Invalidate All Register (SLBIA_An) for a PSL MMU clears the V bit of SLB entry 0. This differs from the Power ISA slbia instruction, which does not clear the V bit of SLB entry 0.  PSL implementations can only implement the lower bit of the IH field. The PSL does not recognize hints that involve when the implementation-specific lookaside information is created based on the MSR value.


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