Revision history   OpenPOWER Library

 10.2.10. PSL Translation Fault Control Register (PSL_TFC_An)

 The PSL Translation Fault Control Register (PSL_TFC_An) allows system software to govern the operation of a single slice of the PSL.

 Setting the Restart (R) bit of this register causes the PSL transaction with a pending translation fault to be reissued. Hardware resets PSL_TFC_An[R] automatically after a pending PSL command is reissued and the corresponding status bit in the PSL_DSISR_An is reset.

 Setting the Continue (C) bit of this register causes the PSL to resume normal operation and report that the pending PSL command has been aborted. Hardware resets PSL_TFC_An[C] automatically after a pending PSL resumes and notifies the AFU that the command has been aborted and the corresponding status bit in the PSL_DSISR_An is reset.

 Setting the Address Error (AE) bit of this register causes the PSL to resume operation and report an address error for the pending PSL command to the AFU. Hardware resets PSL_TFC_An[AE] automatically after a pending PSL resumes and notifies the AFU of the addressing error and the corresponding status bit in the PSL_DSISR_An is reset.

 Setting the Acknowledge (A) bit of this register informs the PSL that system software has acknowledged the nontranslation fault interrupts reported using the PSL_DSISR_An (PSL error, AFU error, and operating-system context warning). Hardware resets the corresponding status bits in the PSL_DSISR_An when the PSL_TFC_An[A] bit is written to a '1'.

 The restart operation is only effective if the PSL command queue is in normal queue operational status. Software must set PSL_TFC_An[R] to '1' to resume a PSL command either after one of the faults listed below or after a page protection fault has been indicated.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P2_Base |P2(n)) + x'0078'; where n is an AFU number.

Reserved

A

C

AE

R

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

  

Bits

Field Name

Description

 0:27

 Reserved

 Reserved.

 28

 A

 Acknowledge interrupt.

 Resets the nontranslation fault status bits in the PSL_DSISR_An.

Note: This bit is write-only. A read of the PSL_TFC_An always returns '0' for this bit

0

Nontranslation fault interrupts not acknowledged.

1

Write: Acknowledge the nontranslation faults

(PSL error, AFU error, and operating-system context warning.

Read: Always returns '0'.

 29

 C

 Continue.

Current translation fault is not resolved and must be retried at a later time.

Note: This bit must be set to '1' to restart the PSL and indicate that the current PSL transaction that caused a translation fault is not resolved. The current transaction is aborted. This bit is automatically reset by hardware after the PSL has resumed and indicated a command abort to the AFU.

0

No PSL command continue requested.

1

Write: Restart the PSL with the next transaction (current transaction aborted).

Read: PSL waiting to continue.

 30

 AE

 Address error on the PSL transaction caused the translation fault.

Note: This bit must be set to '1' to restart the PSL and indicate an address error occurred on the PSL transaction that caused a translation fault. This bit is automatically reset by hardware after the PSL has resumed and indicted an address error to the AFU.

0

No PSL command address error requested.

1

Write: Restart the PSL command with an addresss error.

Read: PSL address error pending.

 31

 R

 Restarts the PSL transaction that caused the translation fault.

Note: This bit must be set to '1' to restart the PSL transaction that caused a translation fault. This bit is automatically reset by hardware after the PSL command has been resumed.

0

No PSL command restart requested.

1

Write: Restart the PSL command.

Read: PSL command reissue pending.

 32:63

 Reserved

 Reserved.


loading table of contents...