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 10.2.3.1. Accelerator Utilization Record Pointer Zero Register (AURP0_An) 

 The Accelerator Utilization Record Pointer Zero Register (AURP0_An) contains the upper virtual address, in main storage, of a 64-bit process utilization record (AUR). The PSL increments the AUR value and atomically updates the memory location at the completion of a context time interval.

 This register is initialized by the operating system or from the process element. The process element information is used when the PSL scheduled processes area is enabled (PSL_SPAP_An[V] = '1').

 When the AFU is operating in a virtualized programming model, the data returned when reading this register is indeterminate. CAIA-compliant devices should return the corresponding process element data when an interrupt is pending for diagnostic purposes.

 This facility is optional. System software can detect if this feature is supported by writing x'FF80000000003FFF' to this register and reading back the contents. If a value of zero is returned, this feature is not supported. Any nonzero value indicates that the feature is supported.

 The value written to the Accelerator Utilization Record Pointer Register is implementation specific.

 There is one register for each PSL slice. Access to these registers should be privileged. These registers must be accessed using a single 64-bit store operation.

Access Type

Read/Write

 Base Address Offset

 (P2_Base | P2(n)) + x'0010'; where n is an AFU number.

B

KS

KP

N

L

C

TA

LP

Reserved

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

AURVA_U

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Bits

Field Name

Description

 0:1

 B

 Segment size selector.

 The segment size selector defines the size of the segment containing the accelerator utilization record.

 2

 KS

 Supervisor (privileged) state storage key (tags inactive).

 For more information about the KS bit, see the SLB entry section in the Power ISA, Book III .

 3

 KP

 Problem state storage key.

 For more information about the KP bit, see the SLB entry section in the Power ISA, Book III .

 4

 N

 No-execute segment if N = '1'.

 For more information about the N bit, see the SLB entry section in the Power ISA, Book III .

 5

 L

 Virtual page size selector bit 0.

 For more information about the L bit, see the SLB entry section in the Power ISA, Book III .

 6

 C

 Class.

 For more information about the C bit, see the SLB entry section in the Power ISA, Book III .

 7

 Reserved

 Reserved.

 8:9

 LP

 Virtual page size selector bits 1:2.

 For more information about the LP field, see the SLB Entry section in the Power ISA, Book III .

 10:49

 Reserved

 Set to zeros.

 50:63

 AURVA_U

 Upper bits of the 78-bit virtual address pointer to the accelerator utilization record for the corresponding AFU.


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