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 12.2.1. MSI-X Capability Structure

 Table 12.2, “CAIA MSI-X Capability Structure” is the MSI-X capability structure for a CAIA-compliant accelerator.

 

Table 12.2. CAIA MSI-X Capability Structure

Index CP +

Configuration Data

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 0

 Message Control

 Next Capability Pointer

 Capability ID

 4

 Table Offset

 BIR

 8

 PBA Offset

 BIR

Power Service Layer Implementation Detail:

Table Offset || BIR (offset x'4') = x'8002'; MSI-X Table located at offset x'8000' from BAR 2 (Privileged 2 area).
PBA Offset || BIR (offset x'8') = x'7F02'; pending bit array located at offset x'7F00' from BAR 2 (Privileged 2 area).

Note: The MSI-X table and PBA offsets are set in the MSI-X capability structure and point to a valid MMIO location under the base address selected by the BIR field. The values of the MSI-X table and PBA offsets are implementation dependent.


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