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 8.1. Interrupt Types

 Table 8.1, “Interrupt Types” list the types of interrupts that can be received by system software and the interrupt vector table entry (IVTE) used by the PSL when presenting the interrupt. In the comment column, registers containing additional information about the interrupt are provided.

 

Table 8.1. Interrupt Types

Interrupt Type

PSL_DSISR_An

PSL_SERR_An

IVTE

Comment

DS

DM

ST

UR

PE

AE

OC

M

P

A

S

K

HC

 Data Segment

 1

 0

 0

 0

 -

 -

 -

 -

 -

 -

 -

 -

 -

 IVTE0[a]

 Data segment fault.

 The faulting EA is reported in PSL_DAR_An. The process handle for the faulting process is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written.

 Data Storage

 0

 1

 0

 0

 -

 -

 -

 1

 0

 0

 S[b]

 0

 -

 IVTE0[a]

 Page fault or mapping fault.

 The faulting EA is reported in PSL_DAR_An. The process handle for the faulting process is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register.

 0

 1

 0

 0

 -

 -

 -

 0

 P[c]

 A[d]

 S[b]

 K[e]

 -

 IVTE0[a]

 Protection fault or access fault.

 The faulting EA is reported in PSL_DAR_An. The process handle for the faulting process is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register.

 Segment Table Pointer

 0

 0

 1

 0

 -

 -

 -

 1

 0

 0

 0

 0

 -

 IVTE0[a]

 Page fault or mapping fault.

 The faulting VA is reported in SSTP0_An || SSTP1_An. The process handle for the faulting process is contained in the PSL_PEHandle_An register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register.

 0

 0

 1

 0

 -

 -

 -

 0

 P[c]

 0

 0

 0

 -

 IVTE0[a]

 Protection fault or access fault.

 The faulting VA is reported in SSTP0_An || SSTP1_An. The process handle for the faulting process is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register.

 There is no key protection on the segment table pointer.

 Accelerator Utilization Record

 0

 0

 0

 1

 -

 -

 -

 1

 0

 0

 S[b]

 0

 -

 IVTE0[a]

 Page fault or mapping fault.

 The faulting VA is reported in AURP0_An || AURP1_An. The process handle for the faulting process is contained in the PSL_PEHandle_An register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register. There is no additional interrupt status information.

 0

 0

 0

 1

 -

 -

 -

 0

 P[c]

 A[d]

 S[b]

 0

 -

 IVTE0[a]

 Protection fault or access fault.

 The faulting VA is reported in AURP0_An || AURP1_An. The process handle for the faulting process is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register. There is no additional interrupt status information.

 There is no key protection on the Accelerator Utilization Record Pointer.

 Hypervisor Context Time Warning

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 1

 ErrIVTE

_Slice

 Warn hypervisor.

 This interrupt is caused when the AFU is not responding to a context save request and the hypervisor context warning interval has expired. The process handle for the process not responding is contained in the PSL_PEHandle_An Register.

 The interrupt status is located in the PSL_SERR Register. The interrupt status is reset when the corresponding interrupt status bit is written to a '1'. There is no additional status information for this interrupt.

 Operating System

Context Time

Warning

 -

 -

 -

 -

 -

 -

 1

 -

 -

 -

 -

 -

 -

 IVTE0[a]

 Warn operating system.

 This interrupt is caused when the AFU is not responding to a context save request and the operating system context warning interval has expired. The process handle for the process not responding is contained in the PSL_PEHandle_An Register.

 The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register. There is no additional interrupt status information.

 PSL Slice Error

 -

 -

 -

 -

 1

 -

 -

 -

 -

 -

 -

 -

 -

 IVTE0[a]

 PSL slice error.

 The PSL error interrupt type is a summary for slice errors reported by the PSL. The number and type of PSL errors is implementation specific.

 The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register. Additional implementation-dependent interrupt status information is provided in the PSL_ErrStat_An Register.

 PSL Error

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 ErrIVTE

 PSL error.

 The PSL error interrupt type is a summary for errors reported by the PSL. The number and type of PSL errors is implementation specific.

 The interrupt status is located in the PSL_ErrIVTE Register. The interrupt status is reset when the corresponding interrupt status bits are written to a '1'. Additional interrupt status information is implementation dependent.

 PSL Slice Error

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 0

 ErrIVTE

_Slice

 PSL error.

 The PSL error interrupt type is a summary for errors reported by the PSL. The number and type of PSL errors is implementation specific.

 The interrupt status is located in the PSL_SERR Register. The interrupt status is reset when the corresponding interrupt status bits are written to a '1'. Additional interrupt status information is implementation dependent.

 AFU Error

 -

 -

 -

 -

 -

 1

 -

 -

 -

 -

 -

 -

 -

 IVTE0[a]

 AFU error.

An AFU error is reported by the PSL when the AFU cannot send an error to its corresponding application. The reason for the interrupt is reported in the AFU_ERR_An Register. The process handle for the process that caused the error is contained in the PSL_PEHandle_An Register.

The PSL_DSISR_An status bit is reset when the corresponding PSL_TFC_An Register is written or the PSL slice is purged by writing the PSL_SCNTL_An Register. Additional interrupt status information is implementation dependent.

 AFU

Interrupt

(level n)

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 -

 IVTEn

 AFU interrupt level n.

 The interrupt status and reset of interrupt status is implementation-dependent. The interrupt source number is calculated as defined in Section 10.1.14, “PSL IVTE Offset Register (PSL_IVTE_Offset_An)”, Section 10.1.15, “PSL IVTE Limit Register (PSL_IVTE_Limit_An)”, and Section B.3, “Interrupt Examples”.

[a] The value for IVTE0 is the value in PSL_IVTE_Offset_An[IVTE_Offset_0]

[b] The PSL_DSISR_An[S] bit is set when the access causing the fault is a write type operation; otherwise, set to '0'.

[c] The PSL_DSISR_An[P] bit is set when the access is not permitted by the page protection state; otherwise, set to '0'.

[d] The PSL_DSISR_An[A] bit is set when a lock type operation is performed to a page marked write-through required or caching inhibited; otherwise, set to '0'.

[e] The PSL_DSISR_An[K] bit is set when the access is not permitted by the virtual page class key protection; otherwise, set to '0'.


   

  


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